DATA VALID INDICATION METHOD AND APPARATUS

• US 20100211733A1
• Filed: 02/19/2009
• Published: 08/19/2010
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Vu, Luyen, Chandrasekhar, Uday, Nobunaga, Dean
• Granted Patent: US 8,386,724 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.

Claims

1. A memory device, comprising:

an interface configured to accept one or more data signals and one or more control signals;

an array of non-volatile memory cells;

a data cache coupled to the array of non-volatile memory cells;

a data synchronization register coupled to the data cache and to the interface, wherein the data synchronization register is configured to receive the one or more data signals accepted at the interface, latch the data signals into a particular number of data groups, designate a status of each data group at least partially in response to one or more of the control signals and transfer the data groups to the data cache; and

wherein the data cache is configured to latch each data group having a first designated status.

2. The memory device of claim 1, wherein the data cache is further configured to reject a data group if the designated status of the data group has a second designated status.

3. The memory device of claim 2, wherein the first designated status is indicative of a valid data status and the second designated status is indicative of an invalid data status.

4. The memory device of claim 1, wherein the data synchronization register is coupled to the interface by one of a parallel communications bus and a serial communications bus.

5. The memory device of claim 1, wherein the data synchronization register is coupled to the data cache by a parallel communications bus.

6. The memory device of claim 1, wherein the data synchronization register comprises one or more data registers each data register configured to store a particular number of bits of data.

7. The memory device of claim 6, wherein the data synchronization register comprises one or more validity registers where the number of validity registers equals the number of data registers.

8. The memory device of claim 7, wherein each validity register is associated with one data register.

9. The memory device of claim 7, wherein each validity register is configured to store one or more bit patterns where each of the one or more bit patterns is indicative of a data group status.

10. The memory device of claim 1, wherein the data synchronization register comprises control circuitry where the control circuitry is configured to receive one or more signals, determine a data group validity status of a first data group in response to the one or more signals and associate the determined data group validity status with the first data group.

11. A non-volatile memory device, comprising:

an interface, wherein the interface is configured to receive one or more memory signals;

an array of memory cells;

a data cache coupled to the array of memory cells;

a plurality of data registers, wherein each data register is configured to store a group of data bits;

a plurality of validity registers, wherein each validity register is associated with one of the plurality of data registers;

control circuitry, wherein the control circuitry is configured to receive one or more memory signals received at the interface, latch memory signals comprising data into the plurality of data registers, generate a validity status value for data latched into each of the plurality of data registers at least partially in response to memory signals received at the interface, store the generated validity status values in the plurality of validity registers and transfer groups of data stored in the plurality of data registers to the data cache; and

wherein the data cache is configured to selectively latch data transferred from the plurality of data registers into the data cache at least partially in response to the generated validity status values stored in the plurality of validity registers.

12. An electronic system, comprising:

a host, wherein the host is configured to generate one or more memory signals;

a memory device coupled to the host and configured to operate in response to the one or more memory signals, comprising;

an interface configured to accept one or more of the memory signals;

an array of non-volatile memory cells;

a data cache coupled to the array of non-volatile memory cells;

a data synchronization register coupled to the data cache and to the interface, wherein the data synchronization register is configured to receive the one or more memory signals accepted at the interface, latch memory signals comprising data into a particular number of data groups, designate a status of each data group at least partially in response to one or more of the memory signals and transfer the data groups to the data cache; and

wherein the data cache is configured to latch each transferred data group having a first designated status in the data cache and prevent each transferred data group having a second designated status from being latched in the data cache.

13. A method of handling data in a memory device, comprising:

receiving data from a data bus coupled to the memory device;

grouping the received data into one or more groups of data;

assigning a data validity status to each of the one or more data groups;

transferring the one or more data groups to a data cache; and

latching a transferred data group in the data cache if the data validity status assigned to the transferred data group has a first value.

14. The method of claim 13, further comprising preventing the data cache from latching a transferred data group if the data validity status assigned to the transferred data group has a second value.

15. The method of claim 14, wherein assigning the data validity status to each of the one or more data groups further comprises assigning one of a valid status and invalid status to each of the one or more data groups.

16. The method of claim 13, further comprising transferring data groups latched in the data cache to a memory array coupled to the data cache.

17. The method of claim 16, wherein transferring data groups latched in the data cache to the memory array coupled to the data cache further comprises writing the data groups latched in the data cache into the memory array.

18. A method of operating a memory device, comprising:

receiving one or more control signals;

receiving data from a data bus coupled to the memory device;

grouping the received data into one or more data groups;

assigning a data group validity status to each of the one or more data groups wherein the validity status is assigned at least in part in response to the one or more control signals;

transferring the one or more data groups to a data cache wherein the data cache is coupled to an array of memory cells; and

latching data groups having a first data group validity status into the data cache.

19. The method of claim 18, further comprising preventing data groups having a second data group validity status from being latched into the data cache.

20. The method of claim 18, further comprising performing a write operation of data groups latched into the data cache, wherein the write operation comprises writing the latched data into the array of memory cells.

21. The method of claim 18, wherein grouping received data into one or more data groups further comprises grouping received data into a particular number of data groups.

22. The method of claim 21, wherein receiving data from a data bus further comprises receiving data from a serial data bus.

23. The method of claim 22, wherein transferring the one or more data groups to the data cache further comprises transferring the one or more data groups to the data cache over a parallel data bus.

24. The method of claim 18, further comprising transferring each assigned validity status to the data cache concurrently with each of the one or more data groups.

25. The method of claim 18, wherein assigning the data group validity status further comprises assigning the data group validity status where a first assigned data group validity status is indicative of a valid data group validity status and a second assigned data group validity status is indicative of an invalid data group validity status.