DIGITAL SIGNAL PROCESSOR (DSP) WITH VECTOR MATH INSTRUCTION

• US 20100211761A1
• Filed: 02/18/2010
• Published: 08/19/2010
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: DASGUPTA, Udayan
• Granted Patent: US 9,015,452 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 2207/5354 Using table lookup, e.g. for digit selection in division by digit recurrence
• CPC Class Codes: G06F 2207/5525 Pythagorean sum, i.e. the square root of a sum of squares
• CPC Class Codes: G06F 7/4806 Computations with complex numbers
• CPC Class Codes: G06F 7/535 Dividing only
• CPC Class Codes: G06F 7/548 Trigonometric functions; Co-ordinate transformations
• CPC Class Codes: G06F 7/552 Powers or roots , e.g. Pythagorean sums
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by the work units.

Claims

1. A digital signal processor (DSP), comprising:

an instruction fetch unit;

an instruction decode unit in communication with the instruction fetch unit; and

a register set and a plurality of work units in communication with the instruction decode unit,

wherein a vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by said work units.

2. The DSP of claim 1 wherein the vector math instruction causes wide-load operations and wide-store operations to be used with the register set wherein

3. The DSP of claim 1 wherein the vector math instruction causes the register set and the work units to perform parallel operations to determine absolute values of numerators and denominators for at least two points.

4. The DSP of claim 1 wherein the vector math instruction causes the register set and the work units to perform parallel operations to create division look-up table (LUT) indexes for at least two points.

5. The DSP of claim 4 wherein the vector math instruction causes the register set and the work units to perform parallel multiply operations using the division LUT for at least two points, wherein NORM and masking operations are implemented to track shifting factors to enable the division LUT indexes to have less precision than the points being operated on.

6. The DSP of claim 1 wherein the vector math instruction is a vector division instruction that causes the register set and the work units to perform parallel operations to create multiplicative factors for at least two points, the multiplicative factors being based on sign values for numerators and denominators.

7. The DSP of claim 1 wherein the vector math instruction is a vector division instruction that causes the register set and the work units to perform parallel operations to determine headrooms and shift-factors for at least two points.

8. The DSP of claim 1 wherein the vector math instruction is a vector a tan 2 instruction that causes the register set and the work units to operate on real parts and imaginary parts of at least two points in parallel.

9. The DSP of claim 1 wherein the vector math instruction is a vector a tan 2 instruction that causes the register set and the work units to perform parallel operations to determine headrooms for denominators of at least two points, and wherein the vector a tan 2 instruction causes the register set and the work units to avoid comparisons and to determine scale factors separately from a division operation.

10. The DSP of claim 1 wherein the vector math instruction is a vector a tan 2 instruction that causes the register set and the work units to perform parallel multiply operations using a division look-up table (LUT) for at least two points.

11. The DSP of claim 1 wherein the vector math instruction is a vector complex magnitude instruction that causes the register set and the work units to perform parallel operations to determine absolute values for at least four points.

12. The DSP of claim 1 wherein the vector math instruction is a vector complex magnitude instruction that causes the register set and the work units to perform parallel operations to determine maximum values and minimum values for at least four points.

13. The DSP of claim 1 wherein the vector math instruction is a vector complex magnitude instruction that causes the register set and the work units to perform parallel operations to pack and store maximum values and minimum values for at least four points.

14. A method for a digital signal processor (DSP) with a register set and work units, the method comprising;

decoding a vector math instruction;

in response to decoding the vector math instruction, aligning input vectors and output vectors with a maximum boundary of the register set; and

in response to decoding the vector math instruction, performing parallel operations with the register set and work units to complete a math function.

15. The method of claim 14 further comprising, in response to decoding the vector math instruction, performing parallel operations with the register set and the work units to determine absolute values of numerators and denominators for at least two points.

16. The method of claim 14 further comprising, in response to decoding the vector math instruction, performing parallel operations with the register set and the work units to create division look-up table (LUT) indexes for at least two points.

17. The method of claim 16 further comprising performing parallel multiply operations using the division LUT for at least two points.

18. The method of claim 14 further comprising, in response to decoding the vector math instruction as a vector division instruction,

performing parallel operations with the register set and the work units to create multiplicative factors for at least two points, the multiplicative factors being based on sign values for numerators and denominators;

and

performing parallel operations with the register set and the work units to determine headrooms and shift-factors for at least two points.

19. The method of claim 14 further comprising, in response to decoding the vector math instruction as a vector a tan 2 instruction,

performing parallel operations with the register set and the work units to separately operate on real parts and imaginary parts of at least two points;

performing parallel operations with the register set and the work units to determine headrooms for denominators of at least two points; and

performing parallel multiply operations with the register set and the work units using a division look-up table (LUT) for at least two points.

20. The method of claim 14 further comprising, in response to decoding the vector math instruction as a vector complex magnitude instruction,

performing parallel operations with the register set and the work units to determine absolute values for at least four points;

performing parallel operations with the register set and the work units to determine maximum values and minimum values for at least four points;

performing parallel operations with the register set to pack and store maximum values and minimum values for at least four points.