Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding
First Claim
1. An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols based on instructions received as a fetch packet, wherein said Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm, wherein said application specific processor comprising:
- a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits;
a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and
an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation;
wherein said LLD slot, said BMU slot and said ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.
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Abstract
An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.
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Citations
10 Claims
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1. An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols based on instructions received as a fetch packet, wherein said Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm, wherein said application specific processor comprising:
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a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits; a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation; wherein said LLD slot, said BMU slot and said ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions. - View Dependent Claims (2, 3)
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4. A method of performing a high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in an application specific processor, said application specific processor comprising:
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a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits; a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation; and a specialized register file components, said specialized register file comprising an optimized number of at least one of read ports and write ports that enables a faster processing of said Viterbi decoding functions, wherein said specialized register file comprising at least one of a De-puncturing Register File, a General Purpose Register file, Primary and Secondary State Metric Register files, and Primary and Secondary Branch Metric Register files, wherein said method comprising; loading channel symbols in an input buffer based on instructions received as a fetch packet; de-puncturing said channel symbols based on a puncturing code rate, said puncturing code rate is at least one of a ½
, ⅔
, ¾
, ⅚
, and ⅞
rates convolution codes;storing de-punctured channel symbols in said De-puncturing Register File; and extracting bits from said De-puncturing Register File to said General Purpose Register File. - View Dependent Claims (5, 6, 7, 8)
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9. A method of generating a trackback address of high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in a Traceback buffer, said method being implemented in an application specific processor, said application specific processor comprising:
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a Load-Store, Logical and De-puncturing (LLD) slot to perform at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function; a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation, wherein said method comprising; loading a base pointer with an InitTraceback pointer; obtaining a best state index based on said best state metric computations from said ACS slot using a general purpose register; selecting an appropriate bit from said best state index based on a threshold indicator bit index, wherein said threshold indicator bit index is stored in a CPU control register (CCR); obtaining a next InitTraceback pointer, wherein said next InitTraceback pointer is obtained by multiplying a constant value constant scaling factor to a value of said appropriate bit being indexed from said best state index using said threshold indicator bit index and adding a base address; performing at least one of a post-increment offset indexing or a post-decrement offset indexing in said Traceback buffer; extracting N decision bits based on a state metric computation, wherein said N bits are extracted using a decision vector loaded from a location by said InitTraceback pointer; appending said N decision bits to derive a Next Best State Index, wherein said N decision bits are appended on a most significant side of said best state index to derive said Next Best State Index for a Traceback in forward Trellis; wherein said N decision bits are appended on a least significant side of said best state index to derive said Next Best State Index for a Traceback in reverse Trellis; shifting N bits of said Best State Index, wherein said N bits are shifted from a least significant side of said Best State Index for said Traceback in forward Trellis; wherein said N bits are shifted from a most significant side of said Best State Index for said Traceback in reverse Trellis; and obtaining decoded bits by concatenating said N bits being shifted. - View Dependent Claims (10)
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Specification