Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding

• US 20100211858A1
• Filed: 02/18/2010
• Published: 08/19/2010
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: Saankhya Labs Pvt Ltd.
• Original Assignee: Saankhya Labs Pvt Ltd.
• Inventors: Bmv, Smitha, Saha, Anindya, Billava, Santhosh, Mallapur, Hemant
• Granted Patent: US 8,255,780 B2
• Time in Patent Office: Days
• US Class Current: 714/792
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/395 using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H03M 13/4169 using traceback H03M13/4192 takes precedence
• CPC Class Codes: H03M 13/6362 by puncturing

Abstract

An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Claims

1. An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols based on instructions received as a fetch packet, wherein said Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm, wherein said application specific processor comprising:

a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits;

a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and

an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation;

wherein said LLD slot, said BMU slot and said ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

2. The application specific processor of claim 1, further comprising at least one of a specialized register file components, said specialized register file components comprising an optimized number of at least one of read ports and write ports that enables a faster processing of said Viterbi decoding functions.

3. The application specific processor of claim 1, wherein said specialized register file comprising at least one of a De-puncturing Register File, a General Purpose Register file, Primary and Secondary State Metric Register files, and Primary and Secondary Branch Metric Register files.

4. A method of performing a high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in an application specific processor, said application specific processor comprising:

a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits;

a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations;

an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation; and

a specialized register file components, said specialized register file comprising an optimized number of at least one of read ports and write ports that enables a faster processing of said Viterbi decoding functions, wherein said specialized register file comprising at least one of a De-puncturing Register File, a General Purpose Register file, Primary and Secondary State Metric Register files, and Primary and Secondary Branch Metric Register files, wherein said method comprising;

loading channel symbols in an input buffer based on instructions received as a fetch packet;

de-puncturing said channel symbols based on a puncturing code rate, said puncturing code rate is at least one of a ½

, ⅔

, ¾

, ⅚

, and ⅞

rates convolution codes;

storing de-punctured channel symbols in said De-puncturing Register File; and

extracting bits from said De-puncturing Register File to said General Purpose Register File.

5. The method of claim 4, further comprising computing at least one of Radix-2, a Radix-4 branch metric values and Squared Euclidean branch metric values for said de-punctured channel symbols in said BMU slot.

6. The method of claim 4, further comprising computing at least one of a Quad Radix-4 and a Dual Radix-4 add-compare-select values in said ACS slot, wherein said ACS slot is a 4 way Single Instruction Multiple Data (SIMD) slot.

7. The method of claim 4, further comprising generating decision bits based on said add-compare-select values and storing said decision bits in a trace back buffer.

8. The method of claim 4, wherein said de-puncturing said channel symbols is enabled using DEPUN instructions.

9. A method of generating a trackback address of high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in a Traceback buffer, said method being implemented in an application specific processor, said application specific processor comprising:

a Load-Store, Logical and De-puncturing (LLD) slot to perform at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function;

a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and

an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation, wherein said method comprising;

loading a base pointer with an InitTraceback pointer;

obtaining a best state index based on said best state metric computations from said ACS slot using a general purpose register;

selecting an appropriate bit from said best state index based on a threshold indicator bit index, wherein said threshold indicator bit index is stored in a CPU control register (CCR);

obtaining a next InitTraceback pointer, wherein said next InitTraceback pointer is obtained by multiplying a constant value constant scaling factor to a value of said appropriate bit being indexed from said best state index using said threshold indicator bit index and adding a base address;

performing at least one of a post-increment offset indexing or a post-decrement offset indexing in said Traceback buffer;

extracting N decision bits based on a state metric computation, wherein said N bits are extracted using a decision vector loaded from a location by said InitTraceback pointer;

appending said N decision bits to derive a Next Best State Index, wherein said N decision bits are appended on a most significant side of said best state index to derive said Next Best State Index for a Traceback in forward Trellis;

wherein said N decision bits are appended on a least significant side of said best state index to derive said Next Best State Index for a Traceback in reverse Trellis;

shifting N bits of said Best State Index, wherein said N bits are shifted from a least significant side of said Best State Index for said Traceback in forward Trellis;

wherein said N bits are shifted from a most significant side of said Best State Index for said Traceback in reverse Trellis; and

obtaining decoded bits by concatenating said N bits being shifted.

10. The method of claim 9, further comprising:

loading a base pointer with said next InitTraceback pointer being obtained;

obtaining a best state index based on a result from said next best state index;

wherein if said Traceback buffer is not fully traversed and said decoded bits are not extracted, said method further comprising;

selecting an appropriate bit from said best state index based on a threshold indicator bit index;

obtaining a next InitTraceback pointer, wherein said next InitTraceback pointer is obtained by multiplying a constant value constant scaling factor to a value of said appropriate bit being indexed from said best state index using said threshold indicator bit index and adding a base address;

performing at least one of a post-increment offset indexing or a post-decrement offset indexing in said Traceback buffer;

extracting N decision bits based on a state metric computation, wherein said N decision bits are extracted using a decision vector loaded from a location by said InitTraceback pointer;

appending said N decision bits to derive a Next Best State Index, wherein said N decision bits are appended on a most significant side of said best state index to derive said Next Best State Index for said Traceback in forward Trellis;

wherein said N decision bits are appended on a least significant side of said best state index to derive said Next Best State Index for said Traceback in reverse Trellis; and

shifting N bits of said Best State Index, wherein said N bits are shifted from a least significant side of said Best State Index for said Traceback in forward Trellis;

wherein said N bits are shifted from a most significant side of said Best State Index for said Traceback in reverse Trellis; and

obtaining decoded bits by concatenating said shifted N bits being shifted.