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Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding

  • US 20100211858A1
  • Filed: 02/18/2010
  • Published: 08/19/2010
  • Est. Priority Date: 02/18/2009
  • Status: Active Grant
First Claim
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1. An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols based on instructions received as a fetch packet, wherein said Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm, wherein said application specific processor comprising:

  • a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits;

    a Branch Metric Compute (BMU) slot that performs at least one of a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; and

    an Add-Compare-Select (ACS) slot that performs at least one of a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation;

    wherein said LLD slot, said BMU slot and said ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

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