DEVELOPMENT VERIFICATION APPARATUS FOR UNIVERSAL CHIP

• US 20100211921A1
• Filed: 05/26/2008
• Published: 08/19/2010
• Est. Priority Date: 05/31/2007
• Status: Abandoned Application

• Current Assignee: Beijing Yudong Technology Development Limited
• Original Assignee: Beijing Transpacific IP Technology Development Limited
• Inventors: Hu, Bo, Yu, DaYong, Zhao, Zhenfeng
• Application Number:
  US12/602,014
• Publication Number:
  US 20100211921A1
• Time in Patent Office: Days
• US Class Current: 716/111
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A development verification apparatus for verification of universal chips, including an object design module for storing and executing the object code of the chip to be verified, a control processing module for executing the control program etc. of the user of the development verification apparatus, a power management module for managing the power and charging the battery, and an extended function module for implementing developing function in various fields.

Claims

1. A development verification apparatus for verifying universal chips, comprising:

an object design module, for storing and executing an object code of a chip to be verified;

a control processing module, coupled to the object design module via a first universal interface, for executing a control program to establish data channels between the object design module and a computer, and generate an excitation signal for activating the object code;

a power management module, for supplying power to the development verification apparatus;

an extended function module, coupled to the object design module via a second universal interface, for establishing data channels between the object design module and an external test equipment; and

the computer, coupled to the control processing module via a serial port, and coupled to the object design module through a universal serial bus (USB) for providing the control program, controlling a progress of verification and displaying a verification result.

2. The development verification apparatus of claim 1, wherein the object design module comprises:

a field programmable gate array (FPGA), for executing the object code of the chip to be verified;

a configuration memory, connected to the FPGA, for storing the object code of the chip to be verified;

a USB controller, coupled to the computer via the USB for control of data transmission between the computer and the object design module;

a clock, connected to the FPGA for generating a clock signal for execution of the object code; and

one or more universal interfaces, for controlling data transmissions between the object design module and other function modules.

3. The development verification apparatus of claim 1, wherein the control processing module comprises:

a microprocessor, connected to the computer via a serial port, for executing the control program and communicating with the computer;

the serial port, connected to the microprocessor and the computer for controlling communications therebetween; and

the first universal interface, controlling communications between the control processing module and other function modules.

4. The development verification apparatus of claim 1, wherein the power management module comprises:

a lithium battery, for powering the development verification apparatus;

a buck direct current (DC) switching power converter, for outputting a voltage lower than the lowest voltage of the lithium battery to power the FPGA;

a boost DC switching power converter, for outputting a voltage higher than the highest voltage of the lithium battery to power a peripheral circuit;

a buck-boost DC switching power converter, for outputting a voltage between the lowest voltage and the highest voltage of the lithium battery to power the FPGA and the microprocessor; and

a battery charging circuit, for charging the lithium battery.

5. The development verification apparatus of claim 1, wherein the extended function module comprises:

a radio frequency (RF) transceiver circuit for signal transmission and reception;

an analog-to-digital and digital-to-analog converter (ADC/DAC), connected to the radio frequency transceiver circuit and the object design module for converting to and from between analog signals in the radio frequency transceiver circuit and digital signals in the object design module; and

the second universal interface, controlling signal communications between the extended function module and other function modules, wherein;

a wireless test signal generated from the object code, is digital-to-analog converted by the ADC/DAC, and modulated and transmitted by the radio frequency transceiver circuit; and

a radio frequency signal received by the RF transceiver circuit is demodulated, analog-to-digital converted by the ADC/DAC, and sent to the object design module.