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DEVELOPMENT VERIFICATION APPARATUS FOR UNIVERSAL CHIP

  • US 20100211921A1
  • Filed: 05/26/2008
  • Published: 08/19/2010
  • Est. Priority Date: 05/31/2007
  • Status: Abandoned Application
First Claim
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1. A development verification apparatus for verifying universal chips, comprising:

  • an object design module, for storing and executing an object code of a chip to be verified;

    a control processing module, coupled to the object design module via a first universal interface, for executing a control program to establish data channels between the object design module and a computer, and generate an excitation signal for activating the object code;

    a power management module, for supplying power to the development verification apparatus;

    an extended function module, coupled to the object design module via a second universal interface, for establishing data channels between the object design module and an external test equipment; and

    the computer, coupled to the control processing module via a serial port, and coupled to the object design module through a universal serial bus (USB) for providing the control program, controlling a progress of verification and displaying a verification result.

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