RIGID SEMICONDUCTOR MEMORY HAVING AMORPHOUS METAL OXIDE SEMICONDUCTOR CHANNELS

• US 20100213458A1
• Filed: 02/23/2009
• Published: 08/26/2010
• Est. Priority Date: 02/23/2009
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Prall, Kirk D.
• Application Number:
  US12/390,703
• Publication Number:
  US 20100213458A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 51/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Rigid semiconductor memory using amorphous metal oxide semiconductor channels are useful in the production of thin-film transistor memory devices. Such devices include single-layer and multi-layer memory arrays of volatile or non-volatile memory cells. The memory cells can be formed to have a gate stack overlying an amorphous metal oxide semiconductor, with amorphous metal oxide semiconductor channels.

Claims

1. A memory device, comprising:

a plurality of memory cells having channels of amorphous metal oxide semiconductor; and

a rigid support material underlying the amorphous metal oxide semiconductor.

2. The memory device of claim 1, wherein the rigid support material is a monocrystalline silicon.

3. The memory device of claim 1, wherein the amorphous metal oxide semiconductor is formed on the rigid support material.

4. The memory device of claim 1, wherein the plurality of memory cells comprises memory cells selected from the group consisting of floating-gate memory cells, nitride read-only memory cells, ferroelectric field-effect transistor memory cells, phase-change memory cells and dynamic random access memory cells.

5. The memory device of claim 1, wherein the amorphous metal oxide semiconductor is an ionic amorphous metal oxide semiconductor.

6. The memory device of claim 5, wherein the ionic amorphous metal oxide semiconductor is selected from the group consisting of indium-doped tin oxide, zinc tin oxide, indium gallium zinc oxide, zinc oxide, tin oxide, indium gallium oxide, indium oxide and cadmium oxide.

7. The memory device of claim 1, further comprising:

a dielectric overlying the plurality of memory cells; and

a second plurality of memory cells having channels of a second amorphous metal oxide semiconductor formed overlying the dielectric.

8. The memory device of claim 7, wherein the amorphous metal oxide semiconductor and the second amorphous metal oxide semiconductor are the same type of amorphous metal oxide semiconductor.

9. The memory device of claim 1, wherein the amorphous metal oxide semiconductor has a sufficient charge carrier density to have a transmittance of less than 70%.

10. The memory device of claim 1, wherein the plurality of memory cells have channels on opposing sides of a pillar of the amorphous metal oxide semiconductor.

11. A method of forming a memory array, comprising:

forming an amorphous metal oxide semiconductor overlying a rigid support material;

forming memory cells using the amorphous metal oxide semiconductor; and

forming source/drain regions of the memory cells in the amorphous metal oxide semiconductor.

12. The method of claim 11, wherein forming an amorphous metal oxide semiconductor comprises forming an amorphous metal oxide semiconductor using a process selected from the group consisting of evaporative deposition, electron beam evaporation, pulsed-laser deposition and sputtering.

13. The method of claim 11, wherein forming the amorphous metal oxide semiconductor comprises forming an ionic amorphous metal oxide semiconductor.

14. The method of claim 13, wherein forming the ionic amorphous metal oxide semiconductor comprises forming an ionic amorphous metal oxide semiconductor selected from the group consisting of indium-doped tin oxide, zinc tin oxide, indium gallium zinc oxide, zinc oxide, tin oxide, indium gallium oxide, indium oxide and cadmium oxide.

15. The method of claim 11, wherein forming the amorphous metal oxide semiconductor comprises forming the amorphous metal oxide semiconductor at a temperature of less than 200°

C.

16. A memory device, comprising:

a rigid support material;

a first layer of memory cells formed using a first amorphous metal oxide semiconductor overlying the rigid support material;

a first dielectric overlying the first layer of memory cells;

a second layer of memory cells formed using a second amorphous metal oxide semiconductor overlying the first dielectric;

a second dielectric overlying the second layer of memory cells;

a data line contact selectively connected to the first layer of memory cells and the second layer of memory cells; and

a source line contact selectively connected to the first layer of memory cells and the second layer of memory cells.

17. The memory device of claim 16, further comprising:

at least one additional layer of memory cells, each at least one additional layer of memory cells formed using an additional amorphous metal oxide semiconductor;

wherein the data line contact is further selectively connected to each at least one additional layer of memory cells; and

wherein the source line contact is further selectively connected to each at least one additional layer of memory cells.

18. The memory device of claim 16, wherein the data line contact is in contact with a first source/drain region of the first amorphous metal oxide semiconductor and passes through a first source/drain region of the second amorphous metal oxide semiconductor, and wherein the source line contact is in contact with a second source/drain region of the first amorphous metal oxide semiconductor and passes through a second source/drain region of the second amorphous metal oxide semiconductor.

19. The memory device of claim 18, wherein the source line contact is further in contact with more than one first source/drain regions of the first amorphous metal oxide semiconductor and passes through more than one first source/drain region of the second amorphous metal oxide semiconductor.

20. The memory device of claim 16, wherein the first amorphous metal oxide semiconductor and the second amorphous metal oxide semiconductor are each ionic amorphous metal oxide semiconductors and are each the same ionic amorphous metal oxide semiconductor.

21. A memory device, comprising:

a rigid support material;

a first NAND string of memory cells formed on a first amorphous metal oxide semiconductor overlying the rigid support material, wherein the first NAND string of memory cells comprises two or more memory cells coupled in series source-to-drain;

a first select line gate formed on the first amorphous metal oxide semiconductor and having a first source/drain region connected to a source/drain region of a memory cell on a first end of the first NAND string of memory cells;

a second select line gate formed on the first amorphous metal oxide semiconductor and having a first source/drain region connected to a source/drain region of a memory cell on a second end of the first NAND string of memory cells;

a first dielectric overlying the first NAND string of memory cells, the first select line gate and the second select line gate;

a second NAND string of memory cells formed on a second amorphous metal oxide semiconductor overlying the rigid support material, wherein the second NAND string of memory cells comprises two or more memory cells coupled in series source-to-drain;

a third select line gate formed on the second amorphous metal oxide semiconductor and having a first source/drain region connected to a source/drain region of a memory cell on a first end of the second NAND string of memory cells;

a fourth select line gate formed on the second amorphous metal oxide semiconductor and having a first source/drain region connected to a source/drain region of a memory cell on a second end of the second NAND string of memory cells;

a second dielectric overlying the second NAND string of memory cells, the third select line gate and the fourth select line gate;

a data line contact connected to a second source/drain region of the first select line gate and a second source/drain region of the second select line gate; and

a source line contact connected to a second source/drain region of the third select line gate and a second source/drain region of the fourth select line gate.

22. The memory device of claim 21, wherein the first NAND string of memory cells and the second NAND string of memory cells each comprise memory cells selected from the group consisting of floating-gate memory cells, nitride read-only memory cells, ferroelectric memory cells and phase-change memory cells.

23. The memory device of claim 21, wherein the first amorphous metal oxide semiconductor and the second amorphous metal oxide semiconductor are each selected from the group consisting of indium-doped tin oxide, zinc tin oxide, indium gallium zinc oxide, zinc oxide, tin oxide, indium gallium oxide, indium oxide and cadmium oxide.

24. A method of forming a memory array, comprising:

forming a first amorphous metal oxide semiconductor overlying a rigid support material;

forming a first NAND string of memory cells using the first amorphous metal oxide semiconductor;

forming a first select line gate having a first source/drain region connected to a source/drain region of a memory cell on a first end of the first NAND string of memory cells;

forming a second select line gate having a first source/drain region connected to a source/drain region of a memory cell on a second end of the first NAND string of memory cells;

forming a first dielectric over the first NAND string of memory cells, the first select line gate and the second select line gate;

forming a second amorphous metal oxide semiconductor overlying the first dielectric;

forming a second NAND string of memory cells using the second amorphous metal oxide semiconductor;

forming a third select line gate having a first source/drain region connected to a source/drain region of a memory cell on a first end of the second NAND string of memory cells;

forming a fourth select line gate having a first source/drain region connected to a source/drain region of a memory cell on a second end of the second NAND string of memory cells;

forming a second dielectric over the second NAND string of memory cells, the third select line gate and the fourth select line gate;

forming a data line contact extending through the second dielectric to at least a surface of the first amorphous metal oxide semiconductor and connected to a second source/drain region of the first select line gate and to a second source/drain region of the third select line gate; and

forming a source line contact extending through the second dielectric to at least a surface of the first amorphous metal oxide semiconductor and connected to a second source/drain region of the third select line gate and to a second source/drain region of the fourth select line gate.

25. The method of claim 24, further comprising:

forming at least one additional NAND string of memory cells, each using an additional amorphous metal oxide semiconductor.