SEMICONDUCTOR STORAGE DEVICE AND METHODS OF PRODUCING IT

• US 20100213525A1
• Filed: 02/11/2010
• Published: 08/26/2010
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Japan Ltd.
• Inventors: Masuoka, Fujio, Arai, Shintaro
• Granted Patent: US 8,212,298 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The present invention provides a semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric layer, wherein: the at least one MOS transistor in the memory cell section comprises a selection transistor, the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other, the first MOS transistor includes a first lower drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a first upper source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed such that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film, the second MOS transistor includes a second lower drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second upper source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed such that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film; and the selection transistor includes a third lower drain or source region formed in the planar semiconductor layer, a third pillar-shaped semiconductor layer formed on the planar semiconductor layer, a third lower source or drain region formed in an upper portion of the third pillar-shaped semiconductor layer, and a third gate electrode formed such that the third gate electrode surrounds a sidewall of the third pillar-shaped semiconductor layer through a third dielectric film, and wherein the semiconductor storage device has a first silicide layer formed thereon to connect at least a part of a surface of the first lower drain or source region of the first MOS transistor and at least a part of a surface of the second lower drain or source region of the second MOS transistor, and a second silicide layer formed on at least a part of a surface of the third lower drain or source region of the selection transistor.

Claims

1. A semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising:

a substrate;

a dielectric film on the substrate; and

a planar semiconductor layer formed on the on-substrate dielectric layer,

wherein;

the at least one MOS transistor in the memory cell section comprises a selection transistor,

the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other,

the first MOS transistor includes a first lower drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a first upper source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed such that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film,

the second MOS transistor includes a second lower drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second upper source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed such that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film; and

the selection transistor includes a third lower drain or source region formed in the planar semiconductor layer, a third pillar-shaped semiconductor layer formed on the planar semiconductor layer, a third lower source or drain region formed in an upper portion of the third pillar-shaped semiconductor layer, and a third gate electrode formed such that the third gate electrode surrounds a sidewall of the third pillar-shaped semiconductor layer through a third dielectric film,

and wherein the semiconductor storage device has a first silicide layer formed thereon to connect at least a part of a surface of the first lower drain or source region of the first MOS transistor and at least a part of a surface of the second lower drain or source region of the second MOS transistor, and a second silicide layer formed on at least a part of a surface of the third lower drain or source region of the selection transistor.

2. The semiconductor storage device as defined in claim 1, wherein the first silicide layer is formed in an area other than an area in which a contact for at least the first lower drain or source region and the second lower drain or source region is formed.

3. The semiconductor storage device as defined in claim 1, further comprising a gate line extending from the third gate electrode, wherein a memory cell of the memory cell section is a cross-point type DRAM cell, wherein the third lower drain or source region forms at least a bit line and the third gate electrode and the gate line extending from the third gate electrode forms at least a word line.

4. The semiconductor storage device as defined in claim 3, further comprising:

a first contact formed on a top surface of the third upper source or drain region of the selection transistor, wherein the capacitor element is formed on a top surface of the first contact;

a second contact formed on a top surface of the first or second upper source or drain region of the at least one MOS transistor in the peripheral circuit section; and

a third contact formed on a top surface of the second contact,

wherein the first contact is formed to have a top surface located at a same height position as that of the top surface of the second contact.

5. A semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising:

a substrate;

a dielectric film on the substrate; and

a planar semiconductor layer formed on the on-substrate dielectric layer,

wherein;

the peripheral circuit section comprises one or more peripheral circuit sections; and

the memory cell section comprises a first memory cell section and a second memory cell section which are arranged on opposite sides of one of the peripheral circuit sections,

wherein;

the first and second memory cell sections are configured such that a plurality of first bit lines from the first memory cell section and a plurality of second bit lines from the second memory cell section are alternately connected to the one peripheral circuit section, in such a manner that each of a plurality of pairs of the alternately connected first and second bit lines are connected to a respective one of a plurality of sense amplifiers provided in the one peripheral circuit section; and

the at least one MOS transistor in the peripheral circuit section comprises a MOS transistor constituting the sense amplifiers, the MOS transistor constituting the sense amplifier comprising a combination of a fourth PMOS transistor and a fourth NMOS transistor, and a combination of a fifth PMOS transistor and a fifth NMOS transistor,

wherein;

the fourth PMOS transistor includes a fourth P-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth P-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film;

the fourth NMOS transistor includes a fourth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film;

the fifth PMOS transistor includes a fifth P-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fifth P-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film; and

the fifth NMOS transistor includes a fifth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fifth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film, and wherein;

the semiconductor storage device has a fourth silicide layer formed thereon to connect at least a part of a surface of the fourth P-type lower drain or source region of the fourth PMOS transistor and at least a part of a surface of the fourth N-type lower drain or source region of the fourth NMOS transistor, a fifth silicide layer formed thereon to connect at least a part of a surface of the fifth P-type lower drain or source region of the fifth PMOS transistor and at least a part of a surface of the fifth N-type lower drain or source region of the fifth NMOS transistor, the semiconductor storage device further comprising a fourth contact formed on the fourth silicide layer, a fifth contact formed on the fifth silicide layer, a sixth contact formed on a fourth gate line which connects respective gate electrodes of the fourth PMOS and NMOS transistors, and an seventh contact formed on a fifth gate line which connects respective gate electrodes of the fifth PMOS and NMOS transistors;

the combination of fourth PMOS and NMOS transistors and the combination of fifth PMOS and NMOS transistors are arranged in adjacent relation to each other and between the first bit line formed as a second metal layer line and the second bit lines each formed as the second metal layer line, the first bit line being connected to the fourth silicide layer through the fourth contact and connected to the fifth gate line through the seventh contact, the second bit line being connected to the fifth silicide layer through the fifth contact and connected to the fourth gate line through the sixth contact;

a power source potential line formed as a first metal layer line and perpendicular to the bit line is connected to an eighth and ninth contacts which are formed on the fourth P-type upper source or drain region of the fourth PMOS transistor and the fifth P-type upper source or drain region of the fifth PMOS transistor respectively; and

a ground potential line formed as the first metal layer line and perpendicular to the bit line is connected to an tenth and eleventh contacts which are formed on the fourth N-type upper source or drain region of the fourth NMOS transistor and the fifth N-type upper source or drain region of the fifth NMOS transistor respectively.

6. The semiconductor storage device as defined in claim 5, wherein the fourth silicide layer is formed in an area other than an area in which a contact for at least the fourth P-type lower drain or source region and the fourth N-type lower drain or source region is formed, or the fifth silicide layer is formed in an area other than an area in which a contact for at least the fifth P-type lower drain or source region and the fifth N-type lower drain or source region is formed.

7. A semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising:

a substrate;

a dielectric film on the substrate; and

a planar semiconductor layer formed on the on-substrate dielectric layer,

wherein;

the peripheral circuit section comprises one or more peripheral circuit sections; and

the memory cell section comprises a third memory cell section and a fourth memory cell section which are arranged on opposite sides of one of the peripheral circuit sections,

wherein;

the third and fourth memory cell sections are configured such that a plurality of third bit lines from the third memory cell section and a plurality of fourth bit lines from the fourth memory cell section are alternately connected to the one peripheral circuit section, in such a manner that each of a plurality of pairs of the alternately connected third and fourth bit lines are connected to a respective one of a plurality of row selection switch circuits provided in the one peripheral circuit section; and

the at least one MOS transistor in the peripheral circuit section comprises a MOS transistor constituting the row selection switch circuits, the MOS transistor constituting the row selection switch circuit comprising a combination of a sixth NMOS transistor and a seventh NMOS transistor,

the sixth NMOS transistor includes a sixth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a sixth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film,

the seventh NMOS transistor includes a seventh N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a seventh N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film, and wherein;

the semiconductor storage device has a sixth silicide layer formed on at least a part of a surface of the sixth N-type lower drain or source region of the sixth NMOS transistor, a seventh silicide layer formed on at least a part of a surface of the seventh N-type lower drain or source region of the seventh NMOS transistor and a sixth gate line which connects the gate electrode of the sixth NMOS transistor and the gate electrode of the seventh NMOS transistor, the semiconductor storage device further comprising a twelfth contact formed on the sixth silicide layer, a thirteenth contact formed on the seventh silicide layer, a fourteenth contact formed on the sixth N-type upper source or drain region and connected to the third bit line, a fifteenth contact formed on the seventh N-type upper source or drain region and connected to the fourth bit line and a sixteenth contact formed on the sixth gate line and connected to a row selection line.

8. A semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising:

a substrate;

a dielectric film on the substrate; and

a planar semiconductor layer formed on the on-substrate dielectric layer,

wherein;

the peripheral circuit section comprises one or more peripheral circuit sections; and

the memory cell section comprises a fifth memory cell section and a sixth memory cell section which are arranged on opposite sides of one of the peripheral circuit sections,

wherein;

the fifth and sixth memory cell sections are configured such that a plurality of fifth bit lines from the fifth memory cell section and a plurality of sixth bit lines from the sixth memory cell section are alternately connected to the one peripheral circuit section, in such a manner that each of a plurality of pairs of the alternately connected fifth and sixth bit lines are connected to a respective one of a plurality of pre-charge circuits provided in the one peripheral circuit section; and

the at least one MOS transistor in the peripheral circuit section comprises a MOS transistor constituting the pre-charge circuits, the MOS transistor constituting the pre-charge circuit comprising a eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor,

wherein;

the eighth NMOS transistor includes a eighth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a eighth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film,

the ninth NMOS transistor includes a ninth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a ninth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film; and

the tenth NMOS transistor includes a tenth N-type lower drain or source region formed in the planar semiconductor layer, a pillar-shaped semiconductor layer formed on the planar semiconductor layer, a tenth N-type upper source or drain region formed in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode formed such that the gate electrode surrounds a sidewall of the pillar-shaped semiconductor layer through a gate dielectric film, and wherein;

the semiconductor storage device has a eighth silicide layer formed on at least a part of a surface of the eighth N-type lower drain or source region of the eighth NMOS transistor, a ninth silicide layer formed on at least a part of a surface of the ninth N-type lower drain or source region of the ninth NMOS transistor and a eighth gate line which connects the respective gate electrodes of the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor, the semiconductor storage device further comprising a seventeenth contact formed on the eighth silicide layer and connected to the fifth bit line, a eighteenth contact formed on the ninth silicide layer and connected to the sixth bit line, and a nineteenth and twentieth contact formed on the eighth and ninth N-type upper source or drain region respectively both of which are connected to a ½

power supply voltage line, and a twenty-first contact formed on the eighth gate line and connected to the pre-charge signal line; and

the eighth N-type lower drain or source region and the tenth N-type lower drain or source region are connected through the eighth silicide layer, and/or the ninth N-type lower drain or source region and the tenth N-type lower drain or source region are connected through the ninth silicide layer.

9. A method of producing a semiconductor storage device which has a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising the steps of:

forming a planar semiconductor layer on a dielectric film on a substrate, and a plurality of pillar-shaped semiconductor layers on the planar semiconductor layer;

isolating the planar semiconductor layer as an element;

forming a drain or source region in the planar semiconductor layer;

thereafter forming a first dielectric film on at least a part of a surface of the resulting product;

forming a conductive film on the first dielectric film;

etching back the first dielectric film and the conductive film;

selectively removing by etching the first dielectric film and the conductive film including a portion thereof corresponding to a portion in which the after-mentioned silicide layer is formed to form a gate electrode formed around each of the pillar-shaped semiconductor layers and a gate line extending from the gate electrode;

forming a source or drain region in an upper portion of each of the plurality of pillar-shaped semiconductor layers to have a same conductivity type as that of the drain or source region;

forming a silicide layer for connecting at least a part of a surface of the drain or source region of each of first MOS transistors and at least a part of a surface of the drain or source region of each of second MOS transistors, wherein each of the first and second MOS transistors is one of a plurality of MOS transistors corresponding to respective ones of the plurality of pillar-shaped semiconductor layers, the first and second MOS transistors are included in the peripheral circuit, and the second MOS transistor has a different conductive type from that of the first MOS transistor;

forming a contact on a top surface of the source or drain region of each of the MOS transistors corresponding to the respective ones of the plurality of pillar-shaped semiconductor layers;

forming a capacitor element on a top surface of the contact formed on the top surface of the source or drain region of each of third ones of the MOS transistors corresponding to the respective ones of the plurality of pillar-shaped semiconductor layers, wherein the third MOS transistors are included in the memory cell section; and

forming an additional contact on a top surface of the contact formed on the top surface of the source or drain region of each of the first and second MOS transistors.

10. The method as defined in claim 9, wherein forming the silicide layer further comprises forming a silicide layer on a surface of the source or drain region of each of the first and second MOS transistors.

11. A method of producing a semiconductor storage device which has a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising the steps of:

forming a planar semiconductor layer on a dielectric film on a substrate, and a plurality of pillar-shaped semiconductor layers on the planar semiconductor layer;

isolating the planar semiconductor layer as an element;

forming a drain or source region in the planar semiconductor layer;

thereafter forming a first dielectric film on at least a part of a surface of the resulting product;

forming a conductive film on the first dielectric film;

etching back the first dielectric film and the conductive film;

selectively removing by etching the first dielectric film and the conductive film including a portion thereof corresponding to a portion in which the after-mentioned silicide layer is formed to form a gate electrode formed around each of the pillar-shaped semiconductor layers and a gate line extending from the gate electrode;

forming a source or drain region in an upper portion of each of the plurality of pillar-shaped semiconductor layers to have a same conductivity type as that of the drain or source region;

thereafter forming a protective film on a surface of the resulting product;

removing by etching the protective film only in the peripheral circuit section;

forming a silicide layer for connecting at least a part of a surface of the drain or source region of each of first MOS transistors and at least a part of a surface of the drain or source region of each of second MOS transistors, wherein each of the first and second MOS transistors is one of a plurality of MOS transistors corresponding to respective ones of the plurality of pillar-shaped semiconductor layers, the first and second MOS transistors are included in the peripheral circuit, and the second MOS transistor has a different conductive type from that of the first MOS transistor;

forming a contact on a top surface of the source or drain region of each of the MOS transistors corresponding to the respective ones of the plurality of pillar-shaped semiconductor layers;

forming a capacitor element on a top surface of the contact formed on the top surface of the source or drain region of each of third ones of the MOS transistors corresponding to the respective ones of the plurality of pillar-shaped semiconductor layers, wherein the third MOS transistors are included in the memory cell section; and

forming an additional contact on a top surface of the contact formed on the top surface of the source or drain region of each of the first and second MOS transistors.

12. The method as defined in claim 11, wherein forming a silicide layer further comprises forming a silicide layer on a surface of the source or drain region of each of the first and second MOS transistors.