Trench Device Structure and Fabrication

• US 20100214016A1
• Filed: 02/24/2009
• Published: 08/26/2010
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Zeng, Jun
• Granted Patent: US 7,989,293 B2
• Time in Patent Office: Days
• US Class Current: 327/574
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.

Claims

1-8. -8. (canceled)

9. A vertical-current-flow device, comprising:

a trench including an insulated gate;

a dielectric layer above said insulated gate; and

a layer of doped polysilicon above said dielectric layer.

10. The vertical-current-flow device of claim 9, further comprising a lightly doped diffusion adjacent said dielectric layer.

11. The vertical-current-flow device of claim 9, wherein said insulated gate is a split gate.

12. The vertical-current-flow device of claim 11, wherein said insulated gate includes a polysilicon layer.

13. The vertical-current flow device of claim 9, further comprising permanent charge in said dielectric layer.

14. The vertical-current-flow device of claim 9, wherein said trench extends into a drain region.

17. The vertical-current-flow device of claim 9, further comprising:

source and body diffusions of opposite conductivity types adjacent a sidewall of said trench;

a drift region positioned to receive majority carriers which have been injected by said source, and which have passed through said body diffusion; and

a drain region positioned to receive majority carriers which have passed through said drift region.

15-16. -16. (canceled)

18-21. -21. (canceled)

22. A method of operating a vertical-current-flow semiconductor device, comprising the actions of:

using an insulated gate in a trench to control inversion of a body diffusion, said trench including a glass layer and a doped polysilicon layer;

in a drift region, receiving majority carriers which have been injected by a source, and which have passed through said body diffusion; and

in a drain region, receiving majority carriers which have passed through said drift region;

wherein said gate is capacitively coupled to control inversion of a portion of said body region.

23. The method of claim 22, wherein said glass layer contains a dopant.

24. The method of claim 23, wherein said majority carriers are electrons.

25. The method of claim 23, further comprising a lightly doped diffusion between said source and said body diffusion.

26. The method of claim 23, wherein said insulated gate is a split gate.

27. The method of claim 22, further comprising permanent charge in said glass layer.

28. The method of claim 26 wherein said split gate includes a polysilicon layer.

29. The method of claim 23, wherein said dopant is a n-type dopant.

30. The method of claim 23, wherein said dopant is a p-type dopant.

31. The method of claim 30, wherein said n-type dopant is phosphorus, arsenic or antimony.

32. The method of claim 30, wherein said p-type dopant is boron.

33. A high-density vertical power device, comprising:

at least one active device area;

at least one buried gate electrode, in a patterned trench within said active device area, which is capacitively coupled to control vertical current flow through semiconductor material adjacent to at least part of said buried gate electrode, between a source which lies alongside said trench and a drain which lies below said trench; and

at least one buried source contact electrode, in said patterned trench, which makes contact to said source;

wherein said buried gate electrode and said buried source contact electrode have patterns which are identical within said active device areas, but differ elsewhere.

34. The high-density vertical power device of claim 38, wherein said buried source contact electrode is entirely within said patterned trench.

35. (canceled)