Adaptive Equalization Using Correlation of Edge Samples With Data Patterns

• US 20100215091A1
• Filed: 12/17/2009
• Published: 08/26/2010
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Palmer, Robert E.
• Granted Patent: US 8,243,783 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03273 with carrier recovery circuitry
• CPC Class Codes: H04L 25/069 by detecting edges or zero crossings
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Claims

2. An integrated circuit to receive an input signal, the integrated circuit comprising:

an equalizer to equalize the input signal to produce an equalized signal;

a sampler to generate a sample at a time associated with an expected logic level transition in a pattern represented by the equalized signal; and

a control circuit to adjust equalization applied by the equalizer dependent upon a frequency represented by the pattern, the control circuit including a detection circuit to detect occurrence of the pattern, the adjustment responsive to the sample.

3. The integrated circuit of claim 2, wherein:

the input signal is a serial signal;

the integrated circuit further comprises a clock data recovery circuit; and

the samples include edge samples also used by a clock data recovery circuit to produce a clock signal to time the sampler.

4. The integrated circuit of claim 2, wherein:

the adjustment of the equalization includes adjustment of input signal voltage to account for differences in spectral content of the pattern relative to other patterns; and

adjustment of the equalization uses a range of amplification factors, with higher frequencies of transitions in the input signal being treated to higher amplification factors.

5. The integrated circuit of claim 2, where the detection circuit includes:

a bit correlator to issue a match signal responsive to detection of a particular data pattern;

a phase detector that uses the sample at the time associated with the expected logic level transition and at least one data sample to determine whether a level crossing represented by the pattern is early or late relative to a timing reference signal; and

equalization logic to issue control settings to the equalizer responsive to the match signal and the determination.

6. The integrated circuit of claim 5, where the timing reference signal is an edge clock signal.

7. The integrated circuit of claim 2, where:

the integrated circuit further includes a clock recovery circuit that uses logic level transitions in the input signal to generate a recovered clock;

the control circuit uses data from the clock recovery circuit representing at least some of the logic level transitions to adjust the equalization dependent upon the frequency represented by the pattern; and

the at least some of the logic level transitions are determining according to whether the detection circuit detects occurrence of the pattern.

8. The integrated circuit of claim 2, where:

the integrated circuit further includes a clock recovery circuit that uses edge samples and data samples to generate a recovered clock;

the clock data recovery circuit detects the logic level transition based upon mismatch between adjacent data samples;

the detection circuit includes a phase detector to determine based on a comparison of an edge sample with at least one data sample whether the logic level transition is early or late relative to a timing reference signal; and

the control circuit is to adjust equalization responsive to whether the logic level transition is early or late.

9. The integrated circuit of claim 8, further comprising a retimer to align the edge samples with the data samples to a common clock domain.

10. The integrated circuit of claim 8, where:

the control circuit includes a counter;

the control circuit increments the counter responsive to an indication that the logic level transition is one of early or late;

the control circuit decrements the counter responsive to an indication that the logic level transition is the other of early or late; and

the control circuit is to adjust equalization responsive to whether the counter saturates with either a high value or a low value.

11. The integrated circuit of claim 2, where:

the input signal is a serial signal;

the integrated circuit further comprises

means for generating a word-clock signal,

a deserializer to deserializer the serial signal according to the word-clock signal; and

the pattern detector is to determine whether an incoming word exhibits one or more particular data patterns.

12. The integrated circuit of claim 2, where:

the input signal is a double data rate signal;

the integrated circuit further comprises

at least four samplers, including a pair of data samplers to respectively sample even and odd data samples, and a pair of edge samplers, to sample respective transitions between even and odd symbols; and

data from each of the at least four samplers used by the control circuit to adjust equalization applied by the equalizer dependent upon a frequency represented by the pattern.

13. The integrated circuit of claim 2, where the pattern is a worst-case data pattern.

14. The integrated circuit of claim 2, where the pattern is at least five bits in length.

15. An integrated circuit to receive an input signal, the integrated circuit comprising:

an equalizer to generate an equalized signal;

a detection circuit to identify occurrence of any of at least two different logic patterns in the equalized signal; and

a control circuit to receive a sample taken at a time associated with an expected logic level transition of a detected one of the plural different logic patterns, the control circuit to adjust equalization applied by the equalizer on a frequency-specific basis in dependence upon the sample and the detected one of the plural different logic patterns.

16. The integrated circuit of claim 15, where the control circuit is also to receive a data sample representing a logic level of the input signal at a time other than at the expected logic level transition, the control circuit to adjust frequency specific equalization applied by the equalizer in dependence upon a comparison of the sample at the time associated with the expected logic level transition and the data sample.

17. The integrated circuit of claim 16, where the control circuit is also to receive a first data sample representing a logic level of a first symbol represented by the input signal and a second data sample representing a logic level of a second symbol represented by the input signal, the expected logic level transition representing transition between the first symbol and the second symbol, the control circuit to adjust the equalization in dependence on a comparison of the sample at the time associated with the expected logic level transition with each of the first data sample and the second data sample.

18. A method of adjusting equalization applied to an input signal by an integrated circuit, the integrated circuit including an equalizer, the method comprising:

equalizing the input signal with the equalizer, to generate an equalized signal;

detecting a first pattern of symbols in the equalized signal;

comparing a sample of the equalized signal at a time associated with an expected logic level transition in the first pattern against a reference; and

adjusting equalization applied by the equalizer based on the comparing, where the adjustment of equalization is specific to a frequency represented by the pattern.

19. The method of claim 18, where:

adjusting equalization includes adjusting equalization for a first frequency represented by the first data pattern;

the method further comprises

detecting a second pattern of symbols in the equalized signal, and

comparing a sample of the equalized signal at a time associated with an expected logic level transition in the second pattern against a reference; and

adjusting equalization further includes also adjusting equalization for a second frequency represented by the second data pattern independent of adjustment of equalization for the first frequency.

20. The method of claim 19, where the sample representing the expected logic level transition in the first pattern and the sample representing the expected logic level transition in the second pattern are compared with the same reference.

21. The method of claim 20, where the same reference is a zero-crossing.

22. A method of adjusting equalization applied to an input signal by an integrated circuit, the integrated circuit including an equalizer, the method comprising:

equalizing the input signal with the equalizer, to generate an equalized signal;

detecting a first pattern of symbols in the equalized signal;

performing logic level transition analysis for the first pattern; and

adjusting equalization applied by the equalizer at a frequency represented by the first pattern based on the logic level transition analysis.

1. (canceled)

23. The method of claim 22, further comprising:

detecting a second pattern of symbols in the equalized signal;

performing logic level transition analysis for the second pattern; and

adjusting equalization applied by the equalizer at a frequency represented by the second pattern based on the logic level transition analysis.

24. The method of claim 22, where:

the method further comprises

using a data clock recovery circuit to generate a recovered clock signal, and

upon detecting the first pattern, using at least one sample from the data clock recovery circuit to determine whether a transition represented by the pattern is early or late relative to an expected edge crossing; and

adjusting the equalization is performed responsive to the determination of whether the transition represented by the pattern is early or late relative to the expected edge crossing.

25. The method of claim 24, where the expected edge crossing is determined according to transitions in an edge clock signal.

26. The method of claim 22, where using a data clock recovery circuit includes using an Alexander phase detector.

27. The method of claim 22, where the first pattern is a specific bit pattern and where detecting the first pattern includes detecting an exact bitwise match between the input signal and the specific bit pattern.

26-1. The method of claim 22, where the first pattern is at least five bits in length.

28. An integrated circuit to receive an input signal, comprising:

an equalizer to equalize the input signal to generate an equalized signal;

a clock data recovery circuit to generate a clock signal from the input signal;

a pattern detector to detect a particular logic pattern in the input signal; and

means for updating parameters used by the equalizer to equalize the input signal at a frequency associated with the particular data pattern by using edge information produced by the clock data recovery circuit at a time associated with detection of the particular logic pattern.