METHOD OF FABRICATING A MICROELECTRONIC STRUCTURE INVOLVING MOLECULAR BONDING

• US 20100216294A1
• Filed: 10/10/2008
• Published: 08/26/2010
• Est. Priority Date: 10/12/2007
• Status: Abandoned Application

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Moulet, Jean-Sébastien, Rabarot, Marc, Tauzin, Aurélie, Dubarry, Christophe
• Application Number:
  US12/682,522
• Publication Number:
  US 20100216294A1
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Method of fabricating a microelectronic structure includes preparing a first structure having a first material different from silicon on a surface thereof and forming at least one covering layer of a second material by IBS (ion beam sputtering) and having a thickness of less than one micron, where the at least one cover layer has a free surface and molecular bonding the free surface to one face of a second structure where the at least one covering layer constitutes a bonding layer for the first and second structures.

Claims

1. A method for fabricating a microelectronic structure, the method comprising:

preparing first structure having a first material on a surface thereof, the first material comprising a non-silicon material,

forming at least one covering layer of a second material comprising an oxide, a nitride or an oxynitride on the surface of the first structure by ion beam sputtering (IBS), the at least one covering layer having a thickness of less than one micron and having a free surface, and

molecular bonding the free surface to one face of a second structure, wherein the at least one covering layer comprises a bonding layer for the first and second structures.

2. The method according to claim 1 further comprising scouring the surface of the first structure inside an enclosure for the ion beam sputtering before forming the at least one covering layer.

3. The method according to claim 1, further comprising forming a further covering layer on the second structure before the molecular bonding.

4. The method according to claim 3, wherein forming the further covering layer comprises forming the covering layer by ion beam sputtering.

5. The method according to claim 3, wherein forming the further covering layer comprises forming the same second material as the first covering layer.

7. The method according to claim 1, wherein forming at least one covering layer of a second material comprises forming an oxide of silicon.

8. The method according to any of claim 1, wherein forming at least one covering layer of a second material comprise forming SiO₂, TiO₂, Ta₂O₅, or HfO₂.

9. The method of claim 1, wherein forming at least one covering layer of a second material comprises forming Si₃N₄, TiN, WN, or CrN.

10. The method according to claim 1, wherein forming at least one covering layer of a second material comprises forming an oxynitride of silicon.

11. The method according to claim 10, wherein relative proportions of oxygen and nitrogen are varied within the thickness of the at least one covering layer.

12. The method according to claim 1 further comprising depositing at least one underlying layer by ion beam sputtering before depositing the at least one covering layer.

13. The method according to claim 12, wherein depositing the at least one underlying layer comprises depositing a metallic material or a metal alloy, and depositing the at least one covering layer comprises depositing an oxide.

14. The method according to claim 1, wherein depositing the at least one covering layer comprises depositing an amorphous material.

15. The method according to claim 1, wherein preparing a first structure having a first material comprises preparing a first structure having a semiconductor material.

16. The method according to claim 1, wherein preparing a first structure having a first material comprises preparing a first structure having a material comprising germanium, gallium nitride, gallium arsenide, lithium tantalate or lithium niobate.

6. The method according to claim further comprising:

implanting ions in one or both of the first and second structures in order to form therein a buried layer of microcavities; and

after molecular bonding the free face, fracturing the first or second structures, or both, the buried layer of microcavities at a temperature less than 400°

C.