METHOD FOR ETCHING 3D STRUCTURES IN A SEMICONDUCTOR SUBSTRATE, INCLUDING SURFACE PREPARATION

• US 20100216308A1
• Filed: 02/24/2010
• Published: 08/26/2010
• Est. Priority Date: 02/25/2009
• Status: Abandoned Application

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Phommahaxay, Alain, Tutunjyan, Nina, Cotrin Teixeira, Ricardo, Van Cauwenberghe, Marc, Verdonck, Patrick
• Application Number:
  US12/711,544
• Publication Number:
  US 20100216308A1
• Time in Patent Office: Days
• US Class Current: 438/690
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching

Abstract

A method is provided for producing 3D structures in a semiconductor substrate using Deep Reactive Ion Etching (DRIE), comprising at least the steps of: providing a substrate, and then grinding the backside of the substrate in order to achieve a thinned substrate, wherein extrusions and native oxides are left after said grinding step, and then performing a surface treatment selected from the group consisting of a wet etching step and a dry etching step in order to remove at least said native oxides and extrusions on the surface of said backside of the substrate which are causes for the grass formation during subsequent etching, and then performing deep reactive ion etching in order to achieve 3D vias.

Claims

1. A method for producing a three-dimensional via in a semiconductor substrate using deep reactive ion etching, comprising:

grinding a backside of a substrate, whereby a thinned substrate having extrusions and native oxides on a surface of the backside of the substrate is obtained;

performing a surface treatment on the substrate, wherein the surface treatment is selected from the group consisting of a wet etching step and a dry etching step, whereby the native oxides and extrusions on the surface of the backside of the substrate are removed; and

performing deep reactive ion etching, whereby a three-dimensional via is obtained.

2. The method of claim 1 wherein the substrate is a silicon wafer.

3. The method of claim 1 wherein the substrate is a processed silicon wafer comprising active devices.

4. The method of claim 1, wherein the surface treatment is a wet etching step performed by a method selected from the group consisting of immersion etching in a solution, spray etching with a solution, and puddle etching with a solution, wherein the solution comprises HNO₃ and HF and at least one of H₂O and acetic acid.

5. The method of claim 4, wherein a ratio of HNO3 (65% conc.) to HF (49% conc.) is from 3:

1 to 1;

2.

6. The method of claim 5, wherein a content of H₂O and acetic acid of the solution is preferably at least the same as a content of other constituents of the solution.

7. The method of claim 4, wherein the solution comprises 1 part HNO₃ (65% conc.), 1 part HF (49%) and 2 parts H₂O.

8. The method of claim 4, wherein the wet etching step is performed for a period of time of from 15 seconds to 2 minutes.

9. The method of claim 1, wherein the surface treatment step is a dry etching step performed using a capacitive coupled plasma or an inductively coupled plasma.

10. The method of claim 1, wherein the capacitive coupled plasma or the inductively coupled plasma comprises one or more fluorine containing gases.

11. The method of claim 10, wherein the one or more fluorine containing gases comprises SF₆

12. The method of claim 10, wherein the capacitive coupled plasma or the inductively coupled plasma further comprises one or more additive gases.

13. The method of claim 12, wherein the one or more additive gases comprises argon.

14. The method of claim 9, wherein the surface treatment step is a dry etching step performed using a capacitive coupled plasma type reactor wherein an absolute value of the bias voltage or of a low frequency component of the applied voltage is 200 V or higher.

15. The method of claim 9, wherein the surface treatment step is a dry etching step performed using an inductively coupled plasma type reactor wherein an absolute value of the bias voltage or of a low frequency component of the applied voltage is 100 V or higher.

16. The method of claim 1, comprising deep reactive ion etching of deep silicon structures in three-dimensional integration of silicon wafers.

17. The method of claim 1, wherein the deep silicon structures are vias.

18. The method of claim 1, wherein a presence of the extrusions and the native oxides would otherwise cause grass formation during subsequent etching of the substrate.