HIGH AVAILABILITY MEMORY SYSTEM

• US 20100217915A1
• Filed: 02/23/2009
• Published: 08/26/2010
• Est. Priority Date: 02/23/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Lastras-Montano, Luis A., O'Connor, James A., Maule, Warren E.
• Granted Patent: US 8,086,783 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 12/0886 Variable-length word access

Abstract

A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.

Claims

1. A memory system comprising:

multiple memory channels, each memory channel comprised of;

at least one memory module comprised of memory devices organized as partial ranks coupled to memory device bus segments, each partial rank including a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments; and

a memory controller in communication with the multiple memory channels, the memory controller distributing an access request across the memory channels to access a full rank, the full rank comprised of at least two of the partial ranks on separate memory channels.

2. The memory system of claim 1 wherein the memory system further comprises one or more checksum memory devices storing checksum data, and the memory controller further comprises an error handler, the error handler calculating a check value as a function of data received in response to the access request and the checksum data associated with the data to determine whether an error exists.

3. The memory system of claim 2 wherein the one or more checksum memory devices are located on common memory modules with the partial ranks, and the checksum data is an error correction code.

4. The memory system of claim 2 further comprising a cache memory with a cache line size equal to an amount of data received, and further wherein the error handler fixes at least one error value in the data received prior to writing the data to the cache memory in response to determining that the error exists.

5. The memory system of claim 2 wherein an error correction memory channel implements error checking across a group of the memory modules selected from the memory channels.

6. The memory system of claim 5 wherein the error checking applies a Reed-Solomon code.

7. The memory system of claim 5 wherein the error checking compensates for insertion and removal of one or more memory modules on one of the memory channels while the memory system remains operational.

8. The memory system of claim 5 wherein the memory system is comprised of four memory channels and the error correction memory channel implementing the error checking across the four memory channels, and each memory module includes two or more of the checksum memory devices.

9. The memory system of claim 1 wherein the partial ranks are concurrently accessible per memory module, enabling the memory controller to concurrently access different addresses on the same memory module.

10. The memory system of claim 1 further comprising:

a buffer device between the memory controller and the memory devices, the buffer device providing a communication interface to distribute the access request to a targeted subset of the memory device bus segments.

11. The memory system of claim 1 wherein at least one of the memory modules includes multiple concurrently accessible partial ranks, and at least one checksum memory device is shared between at least two of the concurrently accessible partial ranks.

12. A method for providing a memory system with high availability, comprising:

configuring the memory system as multiple memory channels accessible in parallel via a memory controller, each memory channel comprised of;

at least one memory module comprised of memory devices organized as partial ranks coupled to memory device bus segments, each partial rank including a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments;

storing checksums calculated across the memory channels;

performing a memory access to a full rank comprised of at least two of the partial ranks on separate memory channels; and

utilizing the checksums to perform error checking and correct one or more error values detected in response to the memory access to the full rank.

13. The method of claim 12 wherein the checksums apply Reed-Solomon codes to correct for a failure in one of the memory channels by erasure marking memory devices that are identified as having incorrect information and feeding the erasure marks to a decoder that is capable of marked erasure decoding.

14. The method of claim 12 further comprising:

configuring the one or more memory modules as multiple concurrently accessible partial ranks, wherein the concurrently accessible partial ranks enable concurrent independent access to the memory devices on the memory modules via independent subchannels per memory channel; and

performing the memory access across the memory channels to one or more of the concurrently accessible ranks.

15. The method of claim 12 wherein the error checking compensates for insertion and removal of one or more memory modules on one of the memory channels while the memory system remains operational.

16. A computer program product for providing a memory system with high availability, the memory system comprising multiple memory channels accessible in parallel via a memory controller, each memory channel comprised of one or more memory modules including multiple semiconductor memory devices, the computer program product comprising a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method comprising:

storing checksums calculated across the memory channels;

performing a memory access across the memory channels to a subset of the semiconductor memory devices on each of the memory channels, wherein the subset is a partial rank of a full rank distributed across the memory channels; and

utilizing the checksums calculated across the memory channels to perform error checking and correct one or more error values detected in response to the memory access.

17. The computer program product of claim 16, wherein one or more memory modules are configured as multiple concurrently accessible partial ranks, wherein the concurrently accessible partial ranks enable concurrent independent access to the semiconductor memory devices on each of the memory modules via independent subchannels per memory channel, and the method facilitated by the computer program product further comprises:

performing the memory access across the memory channels to one or more of the concurrently accessible partial ranks.

18. The computer program product of claim 17 further wherein at least one of the semiconductor memory devices holds a column checksum per concurrently accessible partial rank and the method facilitated by the computer program product further comprises:

utilizing the column checksum to perform error checking and correct one or more error values detected in response to the memory access.

19. A memory system with high availability comprising:

at least two memory modules on separate memory channels, each memory module comprising a partial rank of semiconductor memory devices arranged on the memory module to output a burst of data words in response to an access request, the partial rank having a data width of thirty-two bits, wherein the partial ranks from at least two of the memory channels are combined to form a full rank; and

one or more memory devices to store one or more checksums calculated across the full rank and support error correction for a failure of one or more of the memory modules.

20. The memory system of claim 19 wherein each memory module further comprises:

a checksum memory device, the checksum memory device configured to store a checksum calculated across the semiconductor memory devices of the memory module and adding eight bits in width to the partial rank of the memory module.

21. The memory system of claim 20 wherein the column checksum is an error correction code.

22. A memory module comprising:

at least nine semiconductor memory devices arranged on the memory module with at least eight of the semiconductor memory devices configured as at least two partial ranks to output a burst of data words per partial rank comprising eight bits per data word in response to an access request, and at least one of the semiconductor memory devices is a checksum memory device outputting a checksum value in response to the access request.

23. The memory module of claim 22 wherein the partial ranks are concurrently accessible via independent subchannels on separate busses of a communication link.

24. The memory module of claim 23 wherein the checksum memory device is shared between at least two of the partial ranks.

25. The memory module of claim 23 wherein one of the semiconductor memory devices is a second checksum memory device, and further wherein the checksum device and the second checksum memory device store separate checksums associated with different partial ranks on the memory module.