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MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

  • US 20100217919A1
  • Filed: 09/01/2009
  • Published: 08/26/2010
  • Est. Priority Date: 02/24/2009
  • Status: Active Grant
First Claim
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1. A memory controller configured to perform control for storing and reading data into and out from a NAND-type flash memory section having a plurality of memory cells, the memory controller comprising:

  • a logical-physical address conversion table configured to perform conversion between a physical address which indicates a position of a memory cell in the NAND-type flash memory section, and a logical address which indicates a position of the memory cell in logical space;

    an access number storing section configured to store the number of accesses to read out the data from the memory cell in association with the logical address;

    a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses; and

    a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

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