MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

• US 20100217919A1
• Filed: 09/01/2009
• Published: 08/26/2010
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuji, Hidetaka, Takano, Shuji, Sukegawa, Hiroshi
• Granted Patent: US 9,229,851 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

Claims

1. A memory controller configured to perform control for storing and reading data into and out from a NAND-type flash memory section having a plurality of memory cells, the memory controller comprising:

a logical-physical address conversion table configured to perform conversion between a physical address which indicates a position of a memory cell in the NAND-type flash memory section, and a logical address which indicates a position of the memory cell in logical space;

an access number storing section configured to store the number of accesses to read out the data from the memory cell in association with the logical address;

a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses; and

a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

2. The memory controller according to claim 1, wherein

the refresh processing section performs the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the access number storing section and processing of the storage state checking section are performed for each logical block unit having a same size as the physical block.

3. The memory controller according to claim 1, wherein

the refresh processing section performs the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the access number storing section and processing of the storage state checking section are performed for each logical block group unit which has a plurality of logical blocks each of which has a same size as the physical block.

4. The memory controller according to claim 3, wherein if the storage state of the data which is checked by the storage state checking section is in the predetermined degraded state, the refresh processing section performs the refresh processing when an instruction to perform the refresh processing is given from a host.

5. The memory controller according to claim 3, wherein the storage state checking section reads out the stored data under a condition in which an error is more likely to occur than under a condition of normal data readout.

6. The memory controller according to claim 3, wherein the storage state checking section checks a storage state of data stored in a memory cell in which an error is likely to occur.

7. The memory controller according to claim 3, wherein the refresh processing section performs the refresh processing during an idling time of a host if the storage state of the data checked by the storage state checking section is in the predetermined degraded state.

8. A semiconductor memory device configured to store and read out data, the semiconductor memory device comprising:

a NAND-type flash memory section having a plurality of memory cells;

a logical-physical address conversion table configured to perform conversion between a physical address which indicates a position of a memory cell in the NAND-type flash memory section, and a logical address which indicates a position of the memory cell in logical space;

an access number storing section configured to store the number of accesses to read out the data from the memory cell in association with the logical address;

a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses; and

a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

9. The semiconductor memory device according to claim 8, wherein

the refresh processing section performs the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the access number storing section and processing of the storage state checking section are performed for each logical block unit having a same size as the physical block.

10. The semiconductor memory device according to claim 8, wherein

the refresh processing section performs the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the access number storing section and processing of the storage state checking section are performed for each logical block group unit which has a plurality of logical blocks each of which has a same size as the physical block.

11. The semiconductor memory device according to claim 10, wherein if the storage state of the data which is checked by the storage state checking section is in the predetermined degraded state, the refresh processing section performs the refresh processing when an instruction to perform the refresh processing is given from a host.

12. The semiconductor memory device according to claim 10, wherein the storage state checking section reads out the stored data under a condition in which an error is more likely to occur than under a condition of normal data readout.

13. The semiconductor memory device according to claim 10, wherein the storage state checking section checks a storage state of data stored in a memory cell in which an error is likely to occur.

14. The semiconductor memory device according to claim 10, wherein the refresh processing section performs the refresh processing during an idling time of a host if the storage state of the data checked by the storage state checking section is in the predetermined degraded state.

15. A control method of a semiconductor memory device configured to store and read out data, the control method comprising:

storing the number of accesses for each logical block to which a memory cell belongs, when data is read out from the memory cell which stores the data;

checking a storage state of the data stored in the memory cell which belongs to the logical block, at every predetermined number of accesses; and

performing refresh processing with respect to the memory cell which belongs to the logical block if the storage state of the data is in a predetermined degraded state.

16. The control method of the semiconductor memory device according to claim 15, wherein

the performing comprises performing the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the storing and processing of the checking are performed for each logical block unit having a same size as the physical block.

17. The control method of the semiconductor memory device according to claim 15, wherein

the performing comprises performing the refresh processing for each physical block unit which is a unit of data erasure composed of a predetermined number of the memory cells, and

processing of the storing and processing of the checking are performed for each logical block group unit which has a plurality of logical blocks each of which has a same size as the physical block.

18. The control method of the semiconductor memory device according to claim 17, wherein if the storage state of the data which is checked by the checking is in the predetermined degraded state, the performing comprises performing the refresh processing when an instruction to perform the refresh processing is given from a host.