Memory system and address allocating method of flash translation layer thereof

• US 20100217920A1
• Filed: 12/18/2009
• Published: 08/26/2010
• Est. Priority Date: 02/26/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Jong-uk
• Application Number:
  US12/654,388
• Publication Number:
  US 20100217920A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The memory system includes a flash memory and a memory controller. The flash memory has at least two addresses with different program times. The memory controller is configured to control the flash memory. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory. The assigned address is used to store data of the memory controller in the flash memory.

Claims

1. An address allocating method of a flash translation layer, comprising:

judging whether interruption of a power supply is predicted; and

assigning one of a plurality of addresses having different program times according to a result of the judgment.

2. The address allocating method of claim 1, wherein the assigning assigns an address having a shorter program time from among the plurality of addresses if the judging predicts interruption of the power supply.

3. The address allocating method of claim 1, wherein the judging predicts interruption of the power supply based on sensing a voltage level of at least one of a data line and a power line.

4. The address allocating method of claim 1, wherein the judging predicts interruption of the power supply based on receiving an external power-down command.

5. A memory system comprising:

a flash memory having at least two addresses with different program times; and

a memory controller configured to control the flash memory, wherein

the memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory, where the assigned address is used to store data of the memory controller in the flash memory.

6. The memory system of claim 5, further comprising:

an auxiliary power supply device configured to supply an auxiliary power supply for a first time at the interruption of the power supply.

7. The memory system of claim 5, further comprising:

a power line configured to supply an auxiliary power supply to the flash memory for a first time at the interruption of the power supply;

and a data line configured to provide the data to the flash memory, wherein

the power line is longer in length than the data line.

8. The memory system of claim 7, wherein the memory controller is configured to predict interruption of the power supply based on sensing a voltage level of at least one of the data line and the power line.

9. The memory system of claim 5, wherein,

the flash memory includes a first area having single level cells and a second area having multi-level cells,

the memory controller is configured to store the data in the first area if interruption of the power supply is predicted.

10. The memory system of claim 5, further comprising:

a separate line configured to receive and transmit to the memory controller an external power-down signal indicating interruption of the power supply, where the memory controller is configured to predict interruption of the power supply based on the external power-down signal.

11. The memory system of claim 5, wherein the flash memory comprises:

at least one flash memory having single level cells; and

a plurality of flash memories each having multi-level cells,

wherein the memory controller is configured to store data in the at least one flash memory having the single level cells if interruption of the power supply is predicted.

12. A memory system comprising:

a storage medium including a plurality of storage spaces with different program times; and

a memory controller including a buffer memory for temporarily retaining data to be stored in the storage medium, wherein

the memory controller is configured to predict interruption of a power supply to the storage medium,

the memory controller is configured to control the storage medium such that the data in the buffer memory is stored in a storage space having a shorter program time than that of at least another storage space from the among the plurality of storage spaces if the memory controller predicts interruption of the power supply.

13. The memory system of claim 12, wherein the memory controller further comprises:

a power-down prospector configured to predict interruption of the power supply.

14. The memory system of claim 12, wherein the storage medium includes at least one flash memory.

15. The memory system of claim 12, wherein at least one of the plurality of storage spaces includes single level cells and at least another of the plurality of storage spaces includes multi-level cells.

16. The memory system of claim 12, wherein at least one of the plurality of storage spaces includes cells for storing least significant bits (LSB) of the data and another of the plurality of storage spaces includes cells for storing most significant bits (MSB) of the data.

17. The memory system of claim 12, wherein the memory controller is configured to select one of at least two address allocation protocols based on the predicted interruption of the power supply.

18. The memory system of claim 17, wherein the memory controller is configured to assign an address of the storage medium to the data stored in the buffer memory such that the data in the buffer memory is stored in the storage space having the shorter program time, in accordance with one of the at least two address allocation protocols, if the memory controller predicts interruption of the power supply.

19. The memory system of claim 17, wherein the memory controller assigns an address of the storage medium to the data stored in the buffer memory based on a mapping table, in accordance with one of the at least two address allocation protocols, if the memory controller predicts no interruption of the power supply.

20. The memory system of claim 12, wherein the storage medium, the buffer memory, and the memory controller constitute are included in at least one of a Solid State Drive, a memory card, an MP3 player, a digital camera, a digital television (TV), Personal Digital Assistant (PDA), a printer, a computer, and a moving picture reproducing device.

21. The memory system of claim 12, wherein the memory controller is configured to predict interruption of the power supply based on information provided externally from the memory system.

22. The memory system of claim 12, wherein the memory controller is configured to predict interruption of the power supply based on sensing a voltage level of at least one of a data line providing the data and a power line providing the power supply of the storage medium.