LENGTHENING LIFE OF A LIMITED LIFE MEMORY

• US 20100218070A1
• Filed: 02/24/2009
• Published: 08/26/2010
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, Michele, Lastras-Montano, Luis A., Karidis, John Peter, Mittelholzer, Thomas, Wegman, Mark N.
• Granted Patent: US 8,386,883 B2
• Time in Patent Office: Days
• US Class Current: 714/760
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Abstract

A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology). Each one of the storage cells is arbitrarily individually changeable among the at least two levels, and each of the cells is cost-asymmetric. A controller encodes the identical message in the at least first group using the first way or the second way, based on which way incurs a least cost when writing the message into the at least one cell of the at least first group, given current levels of the at least first group.

Claims

1. A phase-change memory comprising:

a matrix of storage cells, said matrix comprising at least a first group, said at least first group comprising at least one of said storage cells, each of said storage cells comprising a phase change material having at least a first resistance value and a second resistance value, such that said at least first group can have an identical message encoded therein in at least a first way and a second way; and

a controller electrically coupled to said matrix, said controller being configured to encode said identical message in said at least first group using one of said at least first and second ways, based on which of said at least first and second ways causes a least amount of writing cost to said group when writing said message into said group, taking into account current levels of said resistance values of said group.

2. The phase-change memory of claim 1, wherein:

said writing cost comprises damage to a given one of said storage cells being written to;

said phase change material undergoes greater damage from melting than from crystallization; and

said controller chooses said one of said at least first and second ways by choosing said crystallization in preference to said melting.

3. The phase-change memory of claim 1, wherein said writing cost comprises energy cost for writing to a given one of said storage cells being written to, and wherein said controller chooses said one of said at least first and second ways by choosing a lower energy cost in preference to a higher energy cost.

4. The phase-change memory of claim 1 further comprising a decoder configured to recover said message from given levels of said resistance values in said at least first group.

5. A memory comprising:

a matrix of storage cells, said matrix comprising at least a first group, said at least first group comprising at least one of said storage cells, each of said storage cells having at least two levels, such that each of said storage cells can have an identical message encoded therein in at least a first way and a second way, each of said storage cells being arbitrarily individually changeable among said at least two levels, each of said storage cells being asymmetric such that increasing from one of said at least two levels to another of said at least two levels has a different cost than decreasing from said another of said at least two levels to said one of said at least two levels; and

a controller electrically coupled to said matrix, said controller being configured to encode said identical message in said at least first group using one of said first way and said second way, based on which of said first way and said second way incurs a least cost when writing said message into said at least one storage cell of said at least first group, taking into account current values of said levels of said at least first group.

6. The memory of claim 5, wherein:

said at least first group has exactly one of said storage cells,

said identical message is one of M messages to be encoded in said exactly one storage cell of said at least first group;

said exactly one storage cell can be programmed to have N of said levels;

said identical message is encoded in said exactly one storage cell of said at least first group by changing said current value of said storage cell level to a changed value of said storage cell level, such that a remainder of division of said changed value of said storage cell level by M is equal to said identical message; and

said changing of said current values of said storage cell level to said changed value of said storage cell level comprises selecting said change to result in a least total cost.

7. The memory of claim 6, wherein:

said memory comprises a phase change memory;

each of said storage cells comprises a phase change material having a variable resistance; and

a cost of increasing said variable resistance is higher than a cost of decreasing said variable resistance.

8. The memory of claim 6, wherein:

N is a power of two;

M is another power of two, M being less than N;

a binary representation of said message is obtained from a binary representation of said changed storage cell level by dropping y least significant bits from said binary representation of said changed storage cell level;

y=log₂(N−

M); and

said messages comprise consecutive integers from zero to M−

1.

9. The memory of claim 5, wherein said identical message is one of M messages to be encoded in said at least first group, said group comprising n_c given ones of said storage cells, said encoding of said identical message being in accordance with:

10. The memory of claim 9, wherein said selecting of said new values of said levels is responsive to a requirement that a cost for changing said current level values to said new level values is minimized.

11. The memory of claim 9, wherein:

said v_i are consecutive integers;

n_c=M−

1;

said storage cells can be programmed with a level selected from among N of said levels; and

N is divisible by M.

14. A memory system comprising:

an assembly of memory cells comprising at least a first section and a second section, at least said memory cells in said first section being of a kind which degrade with use, said first section of said memory cells being encoded, according to a first endurance coding scheme, to reduce said degradation with said use, said second section of said memory cells not being encoded according to said first endurance coding scheme; and

a controlling module electrically coupled to said assembly, said controlling module being configured to;

write first data, requiring at least one of frequent writing and high reliability, to said first section; and

write second data, not requiring said at least one of frequent writing and high reliability, to said second section.

12. The memory of claim 19, wherein:

said storage cells have N of said levels;

groups of H of said storage cells are grouped together as hypercells; and

given levels in said storage cells of a given one of said hypercells correspond to a hyperlevel in said given one of said hypercells.

13. The memory of claim 12, wherein said given levels of said storage cells in said given one of said hypercells are determined by a Gray code of said hyperlevel.

15. The memory system of claim 14, wherein said assembly of said memory cells comprises a matrix of said memory cells addressed as a single address space, and wherein said controlling module comprises a controller.

16. The memory system of claim 15, wherein:

said controller is configured to perform a READ operation by;

receiving an address to be read from;

determining whether said address to be read from is associated with said first section or said second section;

retrieving content of a memory line associated with said address to be read from;

responsive to determining that said address is associated with said first section, decoding said content of said memory line associated with said address to be read from, according to said first endurance coding scheme, to obtain decoded data; and

outputting said decoded data; and

said controller is configured to perform a WRITE operation by;

receiving an address to be written to and corresponding data to be written;

determine whether said address to be written to is associated with said first section or said second section;

responsive to determining that said address to be written to is associated with said first section, retrieving content of a memory line associated with said address to be written to;

responsive to determining that said address to be written to is associated with said first section, encoding said corresponding data to be written, according to said first endurance coding scheme, to obtain encoded data; and

responsive to determining that said address to be written to is associated with said first section, updating memory content at said address to be written to with said encoded data.

17. The memory system of claim 15, wherein said second section of said memory cells is not endurance coded, further comprising a third section of said memory cells endurance coded according to a second endurance coding scheme, said memory cells in said third section being of a kind which degrade with use, and wherein said controlling module is configured to write third data, requiring one of intermediately frequent writing and intermediate reliability, to said third section according to said second endurance coding scheme.

18. The memory system of claim 15, wherein said second section of said memory cells is endurance coded according to a second endurance coding scheme.

19. The memory system of claim 15, wherein:

all of said cells are of said kind which degrade with use;

said matrix of memory cells is organized as an assembly of memory blocks;

said first section has at least one of quickly mutable data, and data requiring high reliability, stored therein as compared to said second section; and

said controller is configured to interface between said assembly and an external user and to dynamically reconfigure said blocks among said sections.

20. The memory system of claim 14, wherein said first section of said memory cells comprises a first memory and said second section of said memory cells comprises a second memory, and wherein said controlling module comprises:

a controller of said first memory;

a controller of said second memory; and

a unified memory interface electrically coupled to said controller of said first memory and said controller of said second memory;

wherein said controller of said first memory carries out said encoding according to said first endurance coding scheme.

21. The memory system of claim 14, wherein said first section of said memory cells comprises a first memory and said second section of said memory cells comprises a second memory, and wherein said controlling module comprises:

a controller of said first memory;

a controller of said second memory; and

a unified memory interface electrically coupled to said controller of said first memory and said controller of said second memory;

wherein said unified memory interface carries out said encoding according to said first endurance coding scheme.

22. The memory system of claim 16, wherein said controlling module comprises:

a controller of said first section of said memory cells;

a controller of said second section of said memory cells; and

a central processing unit electrically coupled to said controller of said first section of said memory cells and said controller of said second section of said memory cells.

23. A memory system comprising:

a matrix of memory cells organized as a plurality of memory lines, each of said lines comprising a payload portion and a metadata portion, said metadata portion requiring at least one of more frequent update and higher reliability than said payload portion, wherein;

at least those of said memory cells associated with said metadata portions are of a kind which degrade with use;

said memory cells associated with said metadata portions are encoded according to a first endurance coding scheme, to reduce said degradation with said use and thereby achieve said requirement of at least one of more frequent update and higher reliability; and

those of said memory cells associated with said payload portions are not encoded according to said first endurance coding scheme; and

a controller electrically coupled to said matrix.

24. The memory system of claim 23, wherein said metadata portions comprise error correcting code portions and wherein said memory lines are subdivided into sub-lines, and wherein said controller is configured to:

receive a given one of said sub-lines to be updated, and a new content therefor;

read a current content of said given sub-line and associated parity checks;

decode said parity checks according to said first endurance coding scheme;

compute an update to said parity checks;

encode said updated parity checks according to said first endurance coding scheme; and

write updated content into said given one of said sub-lines to be updated and write said updated parity checks into an associated error correcting code portion.

25. A method comprising the steps of:

reading current contents of a counter, stored in a non-volatile memory, said counter being endurance coded according to an endurance code;

decoding said current contents using said endurance decoder to obtain a decoded current contents value;

adding a desired number, having one of a positive and a negative number value, to said decoded current contents value, to obtain a result;

encoding said result, using said endurance code, to obtain an encoded result; and

storing said encoded result, as a new value of said counter, in said nonvolatile memory.