SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100219410A1
• Filed: 02/17/2010
• Published: 09/02/2010
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, AKIMOTO, Kengo, YAMAZAKI, Shunpei
• Granted Patent: US 8,704,216 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer containing insulating oxide,

wherein the oxide semiconductor layer containing insulating oxide has an amorphous structure, and

wherein the oxide semiconductor layer containing insulating oxide is electrically connected to the source electrode layer and the drain electrode layer.

2. The semiconductor device according to claim 1,

wherein the insulating oxide is silicon oxide.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer containing insulating oxide is formed by a sputtering method using a target containing SiO₂ at from 0.1% by weight to 30% by weight.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer and the oxide semiconductor layer containing insulating oxide each contain at least one of indium, tin, and zinc.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer has a region which is between the source electrode layer and the drain electrode layer and whose thickness is smaller than that of a region overlapped with the source electrode layer or the drain electrode layer.

6. The semiconductor device according to claim 1,

wherein a portion of the oxide semiconductor layer containing insulating oxide, which is between the source electrode layer and the drain electrode layer, is etched so that the oxide semiconductor layer is exposed.

7. The semiconductor device according to claim 1,

wherein a channel protective layer formed using an inorganic material is provided over the oxide semiconductor layer.

8. The semiconductor device according to claim 1,

wherein a width in a channel direction of the gate electrode layer is larger than that of either the oxide semiconductor layer containing insulating oxide or the oxide semiconductor layer.

9. The semiconductor device according to claim 1,

wherein a hollow is formed under an end portion of the oxide semiconductor layer containing insulating oxide.

10. The semiconductor device according to claim 1,

wherein an end portion of the oxide semiconductor layer is covered with the oxide semiconductor layer containing insulating oxide.

11. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer;

a buffer layer having n-type conductivity over the oxide semiconductor layer containing insulating oxide; and

a source electrode layer and a drain electrode layer over the buffer layer,

wherein the oxide semiconductor layer containing insulating oxide has an amorphous structure,

wherein a conductivity of the buffer layer is higher than that of the oxide semiconductor layer; and

wherein the oxide semiconductor layer containing insulating oxide is electrically connected to one of the source electrode layer and the drain electrode layer through the buffer layer.

12. The semiconductor device according to claim 11,

wherein the buffer layer is formed using a non-single crystal film formed of an oxide semiconductor.

13. The semiconductor device according to claim 11,

wherein the insulating oxide is silicon oxide.

14. The semiconductor device according to claim 11,

wherein the oxide semiconductor layer containing insulating oxide is formed by a sputtering method using a target containing SiO₂ at from 0.1% by weight to 30% by weight.

15. The semiconductor device according to claim 11,

wherein the oxide semiconductor layer and the oxide semiconductor layer containing insulating oxide each contain at least one of indium, tin, and zinc.

16. The semiconductor device according to claim 11,

wherein the oxide semiconductor layer has a region which is between the source electrode layer and the drain electrode layer and whose thickness is smaller than that of a region overlapped with the source electrode layer or the drain electrode layer.

17. The semiconductor device according to claim 11,

wherein a portion of the oxide semiconductor layer containing insulating oxide, which is between the source electrode layer and the drain electrode layer, is etched so that the oxide semiconductor layer is exposed.

18. The semiconductor device according to claim 11,

wherein a channel protective layer formed using an inorganic material is provided over the oxide semiconductor layer.

19. The semiconductor device according to claims 11,

wherein a width in a channel direction of the gate electrode layer is larger than that of either the oxide semiconductor layer containing insulating oxide or the oxide semiconductor layer.

20. The semiconductor device according to claim 11,

wherein a hollow is formed under an end portion of the oxide semiconductor layer containing insulating oxide.

21. The semiconductor device according to claim 11,

wherein an end portion of the oxide semiconductor layer is covered with the oxide semiconductor layer containing insulating oxide.

22. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor film over the gate insulating layer by a sputtering method;

forming a second oxide semiconductor film containing silicon oxide, over the first oxide semiconductor film, by a sputtering method using a target containing SiO₂;

etching the first oxide semiconductor film and the second oxide semiconductor film to form an oxide semiconductor layer and an oxide semiconductor layer containing SiO₂;

forming a conductive layer over the oxide semiconductor layer containing SiO₂; and

etching the conductive layer to form a source electrode layer and a drain electrode layer,

wherein the target containing SiO₂ contains SiO₂ at from 0.1% by weight to 30% by weight.

23. The method for manufacturing the semiconductor device according to claim 22,

wherein the first oxide semiconductor film and the second oxide semiconductor film are wet-etched, so that the first oxide semiconductor film is side-etched and a hollow is formed under an end portion of the oxide semiconductor layer containing SiO₂.

24. The method for manufacturing the semiconductor device according to claim 22,

wherein the target containing SiO₂ contains SiO₂ at from 1% by weight to 10% by weight.

25. The method for manufacturing the semiconductor device according to claim 22,

wherein the first oxide semiconductor film and the second oxide semiconductor film each contain at least one of indium, tin, and zinc.

26. The method for manufacturing the semiconductor device according to claim 22,

wherein a region which is between the source electrode layer and the drain electrode layer and whose thickness is smaller than that of a region overlapped with the source electrode layer or the drain electrode layer is provided in the oxide semiconductor layer containing SiO₂.

27. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor film over the gate insulating layer by a sputtering method;

etching the first oxide semiconductor film to form an oxide semiconductor layer;

forming a second oxide semiconductor film containing silicon oxide, over the oxide semiconductor layer, by a sputtering method using a target containing SiO₂;

etching the second oxide semiconductor film to form an oxide semiconductor layer containing SiO₂ covering the oxide semiconductor layer;

forming a conductive layer over the oxide semiconductor layer containing SiO₂; and

etching the conductive layer to form a source electrode layer and a drain electrode layer,

wherein the target containing SiO₂ contains SiO₂ at from 0.1% by weight to 30% by weight.

28. The method for manufacturing the semiconductor device according to claim 27,

wherein the target containing SiO₂ contains SiO₂ at from 1% by weight to 10% by weight.

29. The method for manufacturing the semiconductor device according to claim 27,

wherein the first oxide semiconductor film and the second oxide semiconductor film each contain at least one of indium, tin, and zinc.

30. The method for manufacturing the semiconductor device according to claim 27,

wherein a region which is between the source electrode layer and the drain electrode layer and whose thickness is smaller than that of a region overlapped with the source electrode layer or the drain electrode layer is provided in the oxide semiconductor layer containing SiO₂.