FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES

• US 20100219456A1
• Filed: 05/17/2010
• Published: 09/02/2010
• Est. Priority Date: 08/25/2004
• Status: Active Grant

• Current Assignee: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Robert S. Chau, Suman Datta, Uday Shah
• Original Assignee: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Robert S. Chau, Suman Datta, Uday Shah
• Inventors: Shah, Uday, Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman
• Granted Patent: US 8,119,508 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Claims

1. A method comprising:

forming a countersunk trench; and

filling said trench with a metal.

2. The method of claim 1 including forming said trench by selectively removing only a portion of a layer in said trench.

3. The method of claim 2 including forming said layer of two portions one stacked atop the other.

4. The method of claim 3 including forming said trench between two spacers.

5. The method of claim 4 including selectively removing only a portion of said spacers after removing the upper portion of said layer.

6. The method of claim 3 including separating said portions with an etch stop layer.

7. The method of claim 1 including forming a stack of two layers, and forming said trench by first removing one of said layers.

8. The method of claim 7 including forming sidewall spacers bracketing said stacked layers.

9. The method of claim 8 including selectively etching the upper layer of said stacked layers.

10. The method of claim 9 including selectively etching the exposed portion of said sidewall spacer when the upper layer of said stack is removed.

11. The method of claim 10 including selectively etching said exposed upper layer of said stack relative to said lower layer of said stack.

12. The method of claim 11 including using different materials for said layers of said stacks.

13. The method of claim 11 including using a timed etch to remove said upper layer.

14. The method of claim 11 including forming a etch stop layer between said upper and lower layers of said stack.

15. A semiconductor structure comprising:

a substrate;

a gate dielectric over said substrate; and

a metal gate electrode over said gate dielectric, said gate electrode having a T-shaped configuration.

16. The structure of claim 15 wherein said gate electrode includes an upper portion which extends over a lower portion.

17. The structure of claim 16 wherein said gate electrode includes a horizontal upper portion and a vertical lower portion, said upper portion having wings extending away from said lower portion, said wings having opposed upper and lower sides, the lower sides of said wings being curved.

18. A semiconductor structure comprising:

a substrate;

a dielectric material over said substrate;

a patterned layer over said substrate;

a dielectric layer surrounding said patterned layer, a trench being formed in said dielectric layer over said patterned layer; and

a sidewall spacer between said dielectric layer and said patterned layer, said sidewall spacer not extending significantly above said patterned layer.

19. The structure of claim 18 wherein said gate dielectric has a dielectric constant greater than 10.

20. The structure of claim 18 including an etch stop layer over said patterned layer.

21. The structure of claim 18 wherein said patterned layer includes silicon.

22. The structure of claim 18 wherein said patterned layer includes germanium.

23. A method comprising:

forming a patterned layer;

forming a sidewall spacer on said patterned layer; and

eroding said sidewall spacer so that said sidewall spacer has a height substantially less than a height of said patterned layer.

24. The method of claim 23 including using a wet etch to erode said sidewall spacer.

25. The method of claim 23 including depositing an interlayer dielectric over said patterned layer and said eroded sidewall spacer.

26. The method of claim 25 including forming a pair of sacrificial gates adjacent to one another, forming a sidewall spacer on each of said gates and eroding the sidewall spacer on each of said gates, and forming an interlayer dielectric over both of said sacrificial gates, said eroded sidewall spacers facilitating the filling of said interlayer dielectric into a region between said gates.