MOS-Gated Power Devices, Methods, and Integrated Circuits

• US 20100219462A1
• Filed: 11/25/2009
• Published: 09/02/2010
• Est. Priority Date: 12/01/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Granted Patent: US 8,378,416 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.

Claims

1. A semiconductor device comprising:

an insulated trench having a sidewall;

a gate electrode;

a semiconductor body region positioned so that voltage bias applied to the gate electrode can induce inversion in said body region to thereby create a channel;

permanent electrostatic charge positioned in proximity to said sidewall of said trench; and

a conductive shield layer which is positioned above said insulated trench, and

not electrically connected to said gate.

2. The device of claim 1, wherein said permanent electrostatic charge comprises embedded cesium ions.

3. The device of claim 1, wherein said insulated trench, below said shield, is substantially filled with dielectric.

4. The device of claim 1, wherein said shield is taller in height than said gate electrode.

6. The device of claim 1, wherein said shield lies entirely within said trench.

7. The device of claim 1, wherein said shield is wider than said trench.

8. The device of claim 1, further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.

9. The device of claim 1, further comprising a lightly doped diffusion layer adjacent to said trench.

10. The device of claim 1, wherein said trench penetrates from the surface of a semiconductor mass into a p-type layer, and also penetrates therethrough into an n-type drain layer.

11. The device of claim 1, built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.

5. (canceled)

12. A substantially vertical device comprising:

a first-conductivity-type source region;

an insulated trench having an approximately vertical sidewall;

a gate electrode;

a semiconductor body region positioned so that voltage bias applied to the gate electrode can induce inversion in said body region to thereby create a lateral channel;

said body region being positioned to separate said source region from said trench;

a first-conductivity type drain extension region positioned in proximity to said trench, and leading from said channel to said sidewall of said trench;

permanent electrostatic charge positioned near said sidewall in density sufficient to invert at least some second-conductivity semiconductor material adjacent thereto; and

a conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.

14. The device of claim 12, wherein said shield is taller in height than said gate electrode.

16. The device of claim 12, wherein said shield lies entirely within said trench.

17. The device of claim 12, wherein said shield is wider than said trench.

18. The device of claim 12, further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.

19. The device of claim 12, wherein said trench penetrates from the surface of a semiconductor mass into a p-type layer, and also penetrates therethrough into an n-type drain layer.

13. (canceled)

15. (canceled)

20-22. -22. (canceled)

23. A substantially vertical semiconductor device comprising:

an insulated trench;

a surface insulation layer containing at least two physically separated gate electrode portions;

a body region positioned so that a voltage bias applied to one of the gate electrodes will cause an inversion layer in said body region;

permanent charges positioned in said insulation material; and

a conductive shield layer positioned between said gate electrodes within said surface insulation layer.

29. The device of claim 23, further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.

30. The device of claim 23, wherein said trench penetrates from the surface of a semiconductor mass into a p-type layer, and also penetrates therethrough into an n-type drain layer.

32. The device of claim 23, wherein said permanent charges are embedded cesium ions.

24-28. -28. (canceled)

31. (canceled)

33-105. -105. (canceled)