POWER DEVICE STRUCTURES AND METHODS

• US 20100219468A1
• Filed: 11/25/2009
• Published: 09/02/2010
• Est. Priority Date: 12/01/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Granted Patent: US 8,304,329 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling.

Claims

1. A semiconductor device, comprising:

a gate electrode, and a semiconductor body region positioned in proximity to said gate electrode so that voltage bias applied to gate electrode controls the existence of a channel in at least some parts of said body region, to thereby permit conduction through the device;

a trench penetrating a semiconductor volume, and containing insulating material;

permanent electrostatic charges in proximity to sidewalls of said trench;

said semiconductor volume being electrically interposed between said channel and a drain region; and

a conductive shield layer which is not electrically connected to said gate electrode, and which is positioned to be capacitively coupled both to said gate electrode and also to portions of said semiconductor volume which are in proximity to said permanent charges.

2. The device of claim 1, wherein said permanent electrostatic charges are cesium ions.

3. The device of claim 1, wherein said body region is doped p-type, and said permanent electrostatic charges carry positive charge.

4. The device of claim 1, wherein said body region consists essentially of silicon.

5. The device of claim 1, wherein said gate and said shield layer are substantially coplanar.

6. The device of claim 1, wherein said gate and said shield layer are electrically separate portions of a single thin-film layer.

7. The device of claim 1, wherein said gate and said shield layer are both made of a doped polycrystalline semiconductor material.

8. The device of claim 1, wherein said gate and said shield layer both lie within said trench.

9. The device of claim 1, wherein said shield layer is located within said trench, and said gate is located higher than the mouth of said trench.

10. A vertical power device comprising:

a trench containing insulating material;

a gate electrode;

a semiconductor body region positioned so that a voltage bias on the gate electrode can cause an inversion layer in said body region, to thereby permit conduction through the device;

permanent charges in proximity to sidewalls of said trench; and

a conductive shield layer positioned below the level of said gate electrode and within said insulating material.

11. The vertical power device of claim 10, wherein said permanent charges are cesium ions.

12. The vertical power device of claim 10, further comprising a drain region, wherein said conductive shield layer reduces gate-drain capacitance.

13. The vertical power device of claim 10, wherein said body region consists essentially of silicon.

14. The vertical power device of claim 10, wherein the maximum width of said shield layer, in at least one horizontal direction, is less than the maximum width of said gate.

15. The vertical power device of claim 10, further comprising a semiconductor drift region in proximity to said permanent charges, and source and drain electrodes which are electrically separated by at least the series combination of said body region and said drift region.

16. A vertical semiconductor device comprising:

a trench containing insulating material;

one or more gate electrodes within said trench, wherein at least part of said insulating material lies between two portions of said gate electrodes within said trench;

a semiconductor body region positioned so that a voltage bias on said gate electrodes can cause an inversion layer in said body region; and

permanent charges included in said insulating material.

17. The vertical semiconductor device of claim 16, wherein said permanent charges cause an inversion layer in at least some semiconductor material which is adjacent to said trench.

18. The vertical power device of claim 16, wherein said permanent charges are cesium ions.

19. The vertical power device of claim 16, further comprising a drain region, wherein said conductive shield layer reduces gate-drain capacitance.

20. The vertical power device of claim 16, wherein said body region consists essentially of silicon.

21-54. -54. (canceled)