METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF

• US 20100219481A1
• Filed: 01/08/2010
• Published: 09/02/2010
• Est. Priority Date: 01/09/2009
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: IMEC International, Panasonic Corporation (Panasonic Holdings Corporation), Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Sengoku, Naohisa, Tseng, Joshua, Okuno, Yasutoshi, Kubicek, Stefan, Ragnarsson, Lars-Ake, Schram, Tom, Hoffmann, Thomas Y.
• Application Number:
  US12/684,803
• Publication Number:
  US 20100219481A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.

Claims

1. A method of manufacturing a dual work function semiconductor device, the method comprising:

defining at least a first region and a second region in a substrate, the first region being electrically isolated from the second region;

forming a first transistor in the first region, the first transistor having a first effective work function, wherein forming the first transistor comprises;

providing a first gate dielectric stack on the substrate, the first gate dielectric stack comprising a first gate dielectric layer and a first gate dielectric capping layer on and in contact with the first gate dielectric layer;

performing a thermal treatment of the first gate dielectric stack so as to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first effective work function;

providing a first metal gate electrode layer on the modified first gate dielectric stack;

patterning the first metal gate electrode layer and modified first gate dielectric stack;

and

after forming the first transistor, forming a second transistor in the second region having a second effective work function being different from the first effective work function.

2. The method according to claim 1, wherein the process of modifying the first gate dielectric stack comprises intermixing of the first gate dielectric layer and the first gate dielectric capping layer.

3. The method according to claim 1, wherein the process of performing a thermal treatment comprises performing an annealing process.

4. The method according to claim 3, wherein the annealing process is performed at a temperature range between 800 degrees Celsius and 1300 degrees Celsius and during a time period in the range of 0.1 second to 30 seconds.

5. The method according to claim 1, wherein the process of performing a thermal treatment comprises performing a thermal treatment in a low oxygen ambient.

6. The method according to claim 1, wherein the process of providing a first gate dielectric capping layer comprises providing an aluminium-based dielectric.

7. The method according to claim 1, wherein the process of forming a second transistor comprises providing a second gate stack in the second region, the second gate stack comprising a second gate dielectric stack and a second metal gate electrode,

8. The method according to claim 7, wherein the process of providing a second gate dielectric stack comprises providing a second gate dielectric and a second gate dielectric capping layer.

9. The method according to claim 8, wherein the second gate dielectric layer comprises the same material as the first gate dielectric layer.

10. The method according to claim 8, wherein the process of providing a second gate dielectric capping layer comprises providing a lanthanide-based dielectric.

11. The method according to claim 1, wherein the first region is a PMOS region and the second region is an NMOS region, and wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

12. The method according to claim 11, wherein the process of providing a first gate dielectric stack comprises providing a Hf-containing gate dielectric layer and an Al-containing gate dielectric capping layer on and in contact with the Hf-containing gate dielectric layer.

13. The method according to claim 1, wherein the first gate dielectric stack has an initial effective oxide thickness (EOTinit) and the modified first gate dielectric stack has a modified effective oxide thickness (EOTmod), wherein the difference between EOTmod and EOTinit is smaller than 30 percent.

14. A dual work function semiconductor device made according to the method of claim 1.

15. A dual work function semiconductor device comprising:

a first transistor in a first region of a substrate, wherein the first transistor comprises a gate dielectric stack comprising an intermixed gate dielectric layer and gate dielectric capping layer, the gate dielectric stack defining the first effective work function of the first transistor, and a first metal gate electrode on the gate dielectric stack; and

a second transistor in a second region of the substrate.

16. The dual work function semiconductor device according to claim 15, wherein the semiconductor device is a CMOS device.

17. The dual work function semiconductor device according to claim 16, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

18. The dual work function semiconductor device according to claim 17, wherein the PMOS transistor comprising an intermixed Hf-containing gate dielectric layer and Al-containing gate dielectric capping layer and a metal gate electrode layer thereon.

19. The dual work function semiconductor device according to claim 17, wherein the NMOS transistor comprising a Hf-containing gate dielectric layer and a La-containing gate dielectric capping layer and another metal gate electrode layer.

20. The dual work function semiconductor device according to claim 18, wherein the NMOS transistor comprising a Hf-containing gate dielectric layer and a La-containing gate dielectric capping layer and another metal gate electrode layer.