RF POWER AMPLIFIER WITH LINEARITY CONTROL

• US 20100219887A1
• Filed: 05/07/2010
• Published: 09/02/2010
• Est. Priority Date: 01/14/2008
• Status: Active Grant

• Current Assignee: Ikuroh Ichitsubo, Koshiro Matsumoto, Masaya Kuwano
• Original Assignee: Ikuroh Ichitsubo, Koshiro Matsumoto, Masaya Kuwano
• Inventors: Matsumoto, Koshiro, Kuwano, Masaya, Ichitsubo, Ikuroh
• Granted Patent: US 9,088,258 B2
• Time in Patent Office: Days
• US Class Current: 330/124.R
• CPC Class Codes: G06F 1/181 Enclosures for portable computers G06F1/1613
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence

Abstract

A linear amplifier circuit includes a multi-stage power amplifier that can amplify an input signal to produce an output signal, and a gain feedback control circuit coupled with the output and the input of the multi-stage power amplifier. An adjacent-channel leakage feedback control circuit can detect the output signal at the output of the multi-stage power amplifier and reduce adjacent-channel leakage in the output signal over an output power range based on the detected output signal.

Claims

1. A linear amplifier circuit, comprising:

a multi-stage power amplifier configured to amplify an input signal to produce an output signal; and

a linearity control circuit configured to control the multi-stage power amplifier to reduce adjacent-channel leakage (ACL) in the output signal.

2. The linear amplifier circuit of claim 1, wherein the spectrum of the output signal comprises a transmission signal in a transmission channel and ACL in an adjacent channel, wherein the linearity control circuit is configured to produce a correction spectral signal in the adjacent channel to reduce ACL.

3. The linear amplifier circuit of claim 1, wherein the spectrum of the output signal comprises a transmission signal in a transmission channel and ACL in an adjacent channel, wherein the linearity control circuit is configured to inject an anti-intermodulation signal in the transmission channel to reduce ACL.

4. The linear amplifier circuit of claim 1, further comprising a biasing control circuit configured to control the biasing of the multi-stage power amplifier, wherein the linearity control circuit is configured to control the biasing control circuit to reduce ACL in the output signal.

5. The linear amplifier circuit of claim 1, wherein the linearity control circuit is configured to extract adjacent-channel leakage around a transmission signal in the spectrum of the output signal, and to control the multi-stage power amplifier to reduce ACL in the output signal.

6. The linear amplifier circuit of claim 5, wherein the linearity control circuit comprises:

a first circuit configured to apply fast Fourier transform (FFT) to the output signal to produce a spectral signal, wherein the spectral signal includes a transmission signal and adjacent-channel leakage next to the transmission signal;

a second circuit configured to extract the adjacent-channel leakage in the spectral signal; and

a third circuit configured to produce a correction spectral signal in response to the extracted adjacent-channel leakage.

7. The linear amplifier circuit of claim 6, wherein the linearity control circuit comprises:

a fourth circuit configured to an inverse fast Fourier transform (IFFT) to the correction spectral signal to produce a correction signal.

8. The linear amplifier circuit of claim 7, wherein the linearity control circuit comprises:

a gain control circuit configured to control the multi-stage power amplifier to reduce adjacent-channel leakage in the output signal in response to the correction signal.

9. The linear amplifier circuit of claim 7, wherein the linearity control circuit comprises:

a phase control circuit configured to control the multi-stage power amplifier to reduce adjacent-channel leakage in the output signal in response to the correction signal.

10. The linear amplifier circuit of claim 1, wherein the multi-stage power amplifier comprises a driver amplifier, a power amplifier in serial connection, and an inter-stage matching circuit coupled between the output of the driver amplifier and the input of the power amplifier.

11. The linear amplifier circuit of claim 1, further comprising:

a first matching circuit connected to the input of the multi-stage power amplifier, the first matching circuit configured to send the input signal to the multi-stage power amplifier; and

a second matching circuit configured to receive the output signal from the output of the multi-stage amplifier before the output signal is output by the linear amplifier circuit, wherein the linearity control circuit is configured to receive the output signal from the output of the second matching circuit.

12. The linear amplifier circuit of claim 1, further comprising:

a gain feedback control circuit coupled with the output and the input of the multi-stage power amplifier, wherein the gain feedback control circuit is configured to detect the output signal at the output of the multi-stage power amplifier and control gain variations of the output signal in an output power range in response to the detected output signal.

13. A linear amplifier circuit, comprising:

a multi-stage power amplifier configured to amplify an input signal to produce an output signal;

a sensing circuit configured to detect at least one of the power, gain, phase of the output signal and to produce a sensing signal; and

a linearity control circuit in communication with the multi-stage power amplifier, wherein the linearity control circuit is configured to reduce, in response to the sensing signal, at least one of gain variations, phase variations, or adjacent-channel leakage in the output signal over an output power range.

14. The linear amplifier circuit of claim 13, wherein the multi-stage power amplifier comprises a driver amplifier and a power amplifier in serial connection, wherein the linearity control circuit is configured to allow gain variations of the power amplifier and gain variations of the driver amplifier to compensate each other.

15. The linear amplifier circuit of claim 14, wherein the driver amplifier exhibits gain expansion in the output power range, and wherein the power amplifier exhibits gain compression in the output power range.

16. The linear amplifier circuit of claim 14, wherein the driver amplifier exhibits gain compression in the output power range, and wherein the power amplifier exhibits gain expansion over the output power range.

17. The linear amplifier circuit of claim 13, wherein the multi-stage power amplifier comprises a driver amplifier and a power amplifier in serial connection, wherein the linearity control circuit is configured to allow phase variations of the power amplifier and phase variations of the driver amplifier to compensate each other.

18. The linear amplifier circuit of claim 17, wherein the driver amplifier exhibits phase expansion in the output power range, and wherein the power amplifier exhibits phase compression over the output power range.

19. The linear amplifier circuit of claim 17, wherein the driver amplifier exhibits phase compression in the output power range, and wherein the power amplifier exhibits phase expansion over the output power range.

20. The linear amplifier circuit of claim 13, wherein the multi-stage power amplifier comprises a driver amplifier and a power amplifier in serial connection, wherein the multi-stage power amplifier comprises an inter-stage matching circuit coupled between the output of the driver amplifier and the input of the power amplifier.