VIDEO ACQUISITION AND PROCESSING SYSTEMS

• US 20100220215A1
• Filed: 08/24/2009
• Published: 09/02/2010
• Est. Priority Date: 01/12/2009
• Status: Abandoned Application

• Current Assignee: Bring Technology Inc.
• Original Assignee: Bring Technology Inc.
• Inventors: Habib, Farooq, Choutov, Dmitri A., Rooyakkers, Albert, Rubinstein, Jorge
• Application Number:
  US12/546,470
• Publication Number:
  US 20100220215A1
• Time in Patent Office: Days
• US Class Current: 348/231.990
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: H04N 19/105 Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• CPC Class Codes: H04N 19/11 among a plurality of spatial predictive coding modes
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/523 with sub-pixel accuracy
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

Embodiments of the present invention are video acquisition and processing systems. One embodiment of the present invention, video acquisition and processing systems include a sensor, image signal processor, and video compression and decompression components fully integrated in a single integrated circuit. The integrated sensor and image signal processor feature highly parallel transmission of image data to the video compression and decompression component. This highly parallel, pipelined, special-purpose integrated-circuit implementation offers cost-effective video acquisition and image data processing and an extremely large computational bandwidth with relatively low power consumption and low-latency for processing video signals.

Claims

1. A video acquisition and processing system comprising:

a sensor;

an image signal processor, the sensor and image signal processor arranged so that the sensor converts detected light into raw image data, the raw image data subsequently converted by the image signal processor into image data having a particular color model and format; and

video compression and decompression component arranged to receive the image data output from the image signal processor and convert the image data into a compressed video-data stream.

2. The system of claim 1 wherein the sensor and image signal processor are implemented in a first integrated circuit and the video compression and decompression component is implemented in a second integrated circuit.

3. The system of claim 2 wherein the first integrated circuit further comprises a pin count of about 40 to about 90 pins.

4. The system of claim 2 wherein the first integrated circuit consumes about 300 to about 720 milliwatts when the first integrated circuit is fabricated with process technology of about 65 nanometers.

5. The system of claim 2 wherein the first integrated circuit consumes about 180 to about 450 milliwatts when the first integrated circuit is fabricated with process technology of about 40 nanometers.

6. The system of claim 2 wherein the first integrated circuit consumes about 100 to about 220 milliwatts when the first integrated circuit is fabricated with process technology of about 32 nanometers.

7. The system of claim 2 wherein the first integrated circuit consumes about 40 to about 150 milliwatts when the first integrated circuit is fabricated with process technology of about 20 nanometers.

8. The system of claim 2 wherein the first integrated circuit is configured with a form factor ranging from about 25 to about 160 square millimeters.

9. The system of claim 2 wherein the second integrated circuit further comprises a pin count of about 50 to about 500 pins.

10. The system of claim 2 wherein the second integrated circuit consumes about 180 to about 720 milliwatts when the second integrated circuit is fabricated with process technology of about 65 nanometers.

11. The system of claim 2 wherein the second integrated circuit consumes about 90 to about 550 milliwatts when the second integrated circuit is fabricated with process technology of about 40 nanometers.

12. The system of claim 2 wherein the second integrated circuit consumes about 70 to about 350 milliwatts when the second integrated circuit is fabricated with process technology of about 32 nanometers.

13. The system of claim 2 wherein the second integrated circuit consumes about 40 to about 200 milliwatts when the second integrated circuit is fabricated with process technology of about 20 nanometers.

14. The system of claim 2 wherein the second integrated circuit is configured with a form factor ranging from about 40 to about 170 square millimeters.

15. The system of claim 2 wherein the first integrated circuit further comprises an image output interface for sending image data in the color model and format output to the video compression and decompression component.

16. The system of claim 1 further comprising a network/transport for sending compressed image data output from the video compression and decompression component in a parallel or a serial structure.

17. The system of claim 16 wherein the compressed video-data stream is output in Ethernet packets.

18. The system of claim 16 wherein the compressed video-data stream is output in at least one of a parallel data stream or a serial data stream.

19. The system of claim 1 wherein the image signal processor further comprises a digital signal processor.

20. The system of claim 1 further comprising memory in electronic communication with the video compression and decompression component, the memory configured with about 8 to about 160 pins.

21. The system of claim 20 wherein the memory consumes about 280 to about 550 milliwatts and has form factor of about 90 to about 160 square millimeters when the memory is fabricated with process technology of about 65 nanometers.

22. The system of claim 20 wherein the memory consumes about 170 to about 320 milliwatts and has form factor of about 50 to about 150 square millimeters when the memory is fabricated with process technology of about 40 nanometers.

23. The system of claim 20 wherein the memory consumes about 80 to about 170 milliwatts and has form factor of about 25 to about 100 square millimeters when the memory is fabricated with process technology of about 32 nanometers.

24. The system of claim 25 wherein the memory consumes about 50 to about 110 milliwatts and has form factor of about 20 to about 80 square millimeters when the memory is fabricated with process technology of about 32 nanometers.

25. The system of claim 1 wherein the video compression and decompression component further comprises integrated memory.

26. The system of claim 1 wherein raw image data is output from the sensor to the image signal processor in macroblocks.

27. The system of claim 1 wherein the video compression and decompression component is configured to receive and decompress a compressed video-data stream.

28. A video acquisition and processing system comprising:

a sensor configured to convert detected light into raw image data; and

video compression and decompression component arranged to receive the raw image data from the sensor, subsequently convert the raw image data into image data having a particular color model and format, and convert the image data into a compressed video-data stream.

29. The system of claim 28 wherein the video compression and decompression component further comprises:

integrated memory; and

a network transport configured to output the compressed image data in a parallel or serial data structure.

30. The system of claim 29 wherein the compressed video-data stream further comprises Ethernet packets.

31. The system of claim 29 wherein the compressed video-data stream further comprises at least one of a serial data stream and a parallel data stream.

32. The system of claim 28 wherein the sensor and video compression and decompression component are implemented in a single integrated circuit.

33. The system of claim 32 wherein the video acquisition and processing system further comprises a pin count of about 40 to about 100 pins.

34. The system of claim 32 wherein the video acquisition and processing system consumes about 250 to about 900 milliwatts when the video acquisition and processing system is fabricated with process technology of about 65 nanometers.

35. The system of claim 32 wherein the video acquisition and processing system consumes about 150 to about 600 milliwatts when the video acquisition and processing system is fabricated with process technology of about 40 nanometers.

36. The system of claim 32 wherein the video acquisition and processing system consumes about 50 to about 300 milliwatts when the video acquisition and processing system is fabricated with process technology of about 32 nanometers.

37. The system of claim 32 wherein the video acquisition and processing system consumes about 20 to about 200 milliwatts when the video acquisition and processing system is fabricated with process technology of about 20 nanometers.

38. The system of claim 32 wherein the video acquisition and processing system is configured with a form factor of about 30 to 150 square millimeters.

39. The system of claim 30 wherein raw image data is output from the sensor to the image signal processor in macroblocks.

40. The system of claim 28 wherein the video compression and decompression component is configured to receive and decompress a compressed video-data stream.

41. A video-camera system comprising:

a lens system for acquiring light reflected from a scene;

a focusing system for focusing the light;

a sensor and image signal processor, the sensor and image signal processor arranged so that the sensor converts detected light into raw image data, the raw image data subsequently converted by the image signal processor into image data with a color model and format; and

video compression and decompression component arranged to receive the image data from the image signal processor output a compressed video-data stream.

42. The system of claim 41 wherein the sensor, image signal processor, and video compression and decompression component is implemented in a single integrated circuit.

43. The system of claim 42 wherein the video acquisition and processing system further comprises a pin count of about 40 to about 90 pins.

44. The system of claim 42 wherein the video acquisition and processing system consumes about 300 to about 720 milliwatts when the video acquisition and processing system is fabricated with process technology of about 65 nanometers.

45. The system of claim 42 wherein the video acquisition and processing system consumes about 180 to about 450 milliwatts when the video acquisition and processing system is fabricated with process technology of about 40 nanometers.

46. The system of claim 42 wherein the video acquisition and processing system consumes about 100 to about 220 milliwatts when the video acquisition and processing system is fabricated with process technology of about 32 nanometers.

47. The system of claim 42 wherein the video acquisition and processing system consumes about 40 to about 150 milliwatts when the video acquisition and processing system is fabricated with process technology of about 20 nanometers.

48. The system of claim 42 wherein the video acquisition and processing system is configured with a form factor ranging from about 25 to about 160 square millimeters.

49. The system of claim 41 wherein the sensor and image signal processor are implemented in a first integrated circuit and the video compression and decompression are implemented in a second integrated circuit.

50. The system of claim 49 wherein the first integrated circuit further comprises a pin count of about 40 to about 90 pins.

51. The system of claim 49 wherein the first integrated circuit consumes about 300 to about 720 milliwatts when the first integrated circuit is fabricated with process technology of about 65 nanometers.

52. The system of claim 49 wherein the first integrated circuit consumes about 180 to about 450 milliwatts when the first integrated circuit is fabricated with process technology of about 40 nanometers.

53. The system of claim 49 wherein the first integrated circuit consumes about 100 to about 220 milliwatts when the first integrated circuit is fabricated with process technology of about 32 nanometers.

54. The system of claim 49 wherein the first integrated circuit consumes about 40 to about 150 milliwatts when the first integrated circuit is fabricated with process technology of about 20 nanometers.

55. The system of claim 49 wherein the first integrated circuit is configured with a form factor ranging from about 25 to about 330 square millimeters.

56. The system of claim 49 wherein the second integrated circuit further comprises a pin count of about 50 to about 500 pins.

57. The system of claim 49 wherein the second integrated circuit consumes about 180 to about 720 milliwatts when the second integrated circuit is fabricated with process technology of about 65 nanometers.

58. The system of claim 49 wherein the second integrated circuit consumes about 90 to about 550 milliwatts when the second integrated circuit is fabricated with process technology of about 40 nanometers.

59. The system of claim 49 wherein the second integrated circuit consumes about 70 to about 350 milliwatts when the second integrated circuit is fabricated with process technology of about 32 nanometers.

60. The system of claim 49 wherein the second integrated circuit consumes about 40 to about 200 milliwatts when the second integrated circuit is fabricated with process technology of about 20 nanometers.

61. The system of claim 49 wherein the second integrated circuit is configured with a form factor ranging from about 40 to about 170 square millimeters.

62. The system of claim 49 wherein the first integrated circuit further comprises an image output interface for sending image data in the color model and format output to the video compression and decompression component.

63. The system of claim 41 further comprising a network/transport for sending compressed video-data stream output from the video compression and decompression component in a parallel or a serial structure.

64. The system of claim 41 wherein the compressed video-data stream is output in Ethernet packets.

65. The system of claim 41 wherein the compressed video-data stream further comprises at least one of a serial data stream and a parallel data stream.

66. The system of claim 41 wherein the image signal processor further comprises a digital signal processor.

67. The system of claim 41 further comprising memory in electronic communication with the video compression and decompression component, the memory configured with about 8 to about 160 pins.

68. The system of claim 67 wherein the memory consumes about 280 to about 550 milliwatts and has form factor of about 90 to about 160 square millimeters when the memory is fabricated with process technology of about 65 nanometers.

69. The system of claim 67 wherein the memory consumes about 170 to about 320 milliwatts and has form factor of about 50 to about 150 square millimeters when the memory is fabricated with process technology of about 40 nanometers.

70. The system of claim 67 wherein the memory consumes about 80 to about 170 milliwatts and has form factor of about 25 to about 100 square millimeters when the memory is fabricated with process technology of about 32 nanometers.

71. The system of claim 67 wherein the memory consumes about 50 to about 110 milliwatts and has form factor of about 20 to about 80 square millimeters when the memory is fabricated with process technology of about 20 nanometers.

72. The system of claim 41 wherein the video compression and decompression component further comprises integrated memory.

73. The system of claim 41 wherein raw image data is output from the sensor to the image signal processor in macroblocks.

74. A handset including a video-camera system configured in accordance with claim 41.