Selective Activation of Programming Schemes in Analog Memory Cell Arrays

• US 20100220509A1
• Filed: 02/28/2010
• Published: 09/02/2010
• Est. Priority Date: 03/01/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri, Sokolov, Dotan, Sommer, Naftali
• Granted Patent: US 8,228,701 B2
• Time in Patent Office: Days
• US Class Current: 365/45
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

Claims

1. A method for data storage, comprising:

defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme;

selecting one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells; and

storing data in the group of the analog memory cells using the selected programming scheme.

2. The method according to claim 1, wherein, upon selecting the first programming scheme, storing the data comprises initially programming the group so as to store given data, programming the at least one memory cell that neighbors the group after initially programming the group, and re-programming the group with the given data after programming the at least one memory cell that neighbors the group.

3. The method according to claim 2, wherein, upon selecting the second programming scheme, storing the data comprises programming the group with the given data only once.

4. The method according to claim 1, wherein, upon selecting the first programming scheme, storing the data comprises pre-compensating respective storage values for storage in the memory cells in the group responsively to the at least one memory cell that neighbors the group, and writing the pre-compensated storage values into the respective memory cells in the group.

5. The method according to claim 4, wherein, upon selecting the second programming scheme, storing the data comprises writing the storage values into the respective memory cells in the group without pre-compensation.

6. The method according to claim 1, wherein the criterion depends on a wear level of the memory cells in the group.

7. The method according to claim 1, wherein the criterion depends on a number of Programming and Erasure (P/E) cycles previously applied to the memory cells in the group.

8. The method according to claim 1, wherein the criterion depends on a number of read errors occurring in one or more read operations from the memory cells in the group.

9. The method according to claim 1, wherein the criterion depends on a temperature of the memory cells in the group.

10. The method according to claim 1, wherein the criterion depends on a supply voltage provided to the memory cells in the group.

11. The method according to claim 1, wherein the criterion depends on a retention time that is expected to occur in the memory cells in the group.

12. The method according to claim 1, wherein the criterion depends on a level of the interference affecting the memory cells in the group.

13. The method according to claim 1, wherein selecting the one of the programming schemes comprises selecting the second programming scheme at a first time, and switching to the first programming scheme at a second time that is later than the first time.

14. The method according to claim 13, and comprising switching from the first programming scheme to the second programming scheme at a third time that is later than the second time.

15. The method according to claim 1, wherein the memory cells are comprised in a memory device, and wherein selection of the one of the programming schemes is performed by a memory controller that is separate from the memory device and connected to the memory device by an interface.

16. The method according to claim 1, wherein the memory cells are comprised in a memory device, and wherein selection of the one of the programming schemes is performed by programming circuitry in the memory device.

17. The method according to claim 1, wherein the memory cells are comprised in a memory device that is connected to a memory controller by an interface, and comprising indicating the selected programming scheme over the interface.

18. A method for data storage, comprising:

defining a first programming scheme that programs a group of analog memory cells while consuming a first peak power, and a second programming scheme that programs the group of the analog memory cells while consuming a second peak power, lower than the first peak power;

selecting one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells; and

storing data in the group of the analog memory cells using the selected programming scheme.

19. The method according to claim 18, wherein the first programming scheme programs the group of the memory cells at a first programming speed, and wherein the second programming scheme programs the group of the memory cells at a second programming speed, slower than the first programming speed.

20. The method according to claim 18, wherein the criterion depends on a number of sets of the memory cells that are programmed concurrently.

21. A method for data storage, comprising:

defining a first programming scheme that programs a group of analog memory cells while permitting immediate aborting of programming the memory cells, and a second programming scheme that programs the group of the analog memory cells without permitting the immediate aborting;

selecting one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells; and

storing data in the group of the analog memory cells using the selected programming scheme.

22. The method according to claim 21, wherein selecting the one of the programming schemes comprises selecting the first programming scheme for programming the group while concurrently reading from another group of the memory cells, and selecting the second programming scheme for programming the group without concurrently reading from any other group of the memory cells.

23. Apparatus for data storage, comprising:

a memory, comprising a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, to define a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.

24. The apparatus according to claim 23, wherein, upon selecting the first programming scheme, the circuitry is configured to initially program the group so as to store given data, to program the at least one memory cell that neighbors the group after initially programming the group, and to re-program the group with the given data after programming the at least one memory cell that neighbors the group.

25. The apparatus according to claim 24, wherein, upon selecting the second programming scheme, the circuitry is configured to program the group with the given data only once.

26. The apparatus according to claim 23, wherein, upon selecting the first programming scheme, the circuitry is configured to pre-compensate respective storage values for storage in the memory cells in the group responsively to the at least one memory cell that neighbors the group, and to write the pre-compensated storage values into the respective memory cells in the group.

27. The apparatus according to claim 26, wherein, upon selecting the second programming scheme, the circuitry is configured to write the storage values into the respective memory cells in the group without pre-compensation.

28. The apparatus according to claim 23, wherein the criterion depends on a wear level of the memory cells in the group.

29. The apparatus according to claim 23, wherein the criterion depends on a number of Programming and Erasure (P/E) cycles previously applied to the memory cells in the group.

30. The apparatus according to claim 23, wherein the criterion depends on a number of read errors occurring in one or more read operations from the memory cells in the group.

31. The apparatus according to claim 23, wherein the criterion depends on a temperature of the memory cells in the group.

32. The apparatus according to claim 23, wherein the criterion depends on a supply voltage provided to the memory cells in the group.

33. The apparatus according to claim 23, wherein the criterion depends on a retention time that is expected to occur in the memory cells in the group.

34. The apparatus according to claim 23, wherein the criterion depends on a level of the interference affecting the memory cells in the group.

35. The apparatus according to claim 23, wherein the circuitry is configured to select the second programming scheme at a first time, and to switch to the first programming scheme at a second time that is later than the first time.

36. The apparatus according to claim 35, wherein the circuitry is configured to switch from the first programming scheme to the second programming scheme at a third time that is later than the second time.

37. The apparatus according to claim 23, wherein the circuitry comprises programming circuitry that is coupled to the memory cells and a memory controller that is separate from the programming circuitry and connected to the programming circuitry by an interface, and wherein selection of the one of the programming schemes is performed by the memory controller.

38. The apparatus according to claim 23, wherein the circuitry comprises programming circuitry that is coupled to the memory cells and a memory controller that is separate from the programming circuitry and connected to the programming circuitry by an interface, and wherein selection of the one of the programming schemes is performed by the programming circuitry.

39. The apparatus according to claim 23, wherein the circuitry comprises programming circuitry that is coupled to the memory cells and a memory controller that is separate from the programming circuitry and connected to the programming circuitry by an interface, and comprising indicating the selected programming scheme over the interface.

40. Apparatus for data storage, comprising:

a memory, comprising a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while consuming a first peak power, to define a second programming scheme that programs the group of the analog memory cells while consuming a second peak power, lower than the first peak power, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.

41. The apparatus according to claim 40, wherein the first programming scheme programs the group of the memory cells at a first programming speed, and wherein the second programming scheme programs the group of the memory cells at a second programming speed, slower than the first programming speed.

42. The apparatus according to claim 40, wherein the criterion depends on a number of sets of the memory cells that are programmed concurrently.

43. Apparatus for data storage, comprising:

a memory, comprising a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while permitting immediate aborting of programming the memory cells, to define a second programming scheme that programs the group of the analog memory cells without permitting the immediate aborting, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.

44. The apparatus according to claim 43, wherein the circuitry is configured to select the first programming scheme for programming the group while concurrently reading from another group of the memory cells, and to select the second programming scheme for programming the group without concurrently reading from any other group of the memory cells.

45. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory that includes a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, to define a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.

46. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory that includes a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while consuming a first peak power, to define a second programming scheme that programs the group of the analog memory cells while consuming a second peak power, lower than the first peak power, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.

47. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory that includes a plurality of analog memory cells; and

circuitry, which is configured to define a first programming scheme that programs a group of the analog memory cells while permitting immediate aborting of programming the memory cells, to define a second programming scheme that programs the group of the analog memory cells without permitting the immediate aborting, to select one of the first and second programming schemes based on a criterion defined with respect to the analog memory cells, and to store data in the group of the analog memory cells using the selected programming scheme.