Reducing Source Loading Effect in Spin Torque Transfer Magnetoresisitive Random Access Memory (STT-MRAM)

• US 20100220516A1
• Filed: 03/02/2009
• Published: 09/02/2010
• Est. Priority Date: 03/02/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhu, Xiaochun, Kang, Seung H., Lee, Kangho
• Granted Patent: US 8,587,993 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

Claims

1. A method comprising:

determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell, the memory cell including the MTJ structure coupled to an access transistor; and

modifying an offset magnetic field that is incident to a free layer of the MTJ structure, wherein the modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

2. The method of claim 1, further comprising adjusting the memory cell from a first configuration having the access transistor electrically coupled to a pinned layer of the MTJ structure to a second configuration having the access transistor electrically coupled to the free layer of the MTJ structure to reduce a source loading effect at the memory cell.

3. The method of claim 2, wherein adjusting the memory cell from the first configuration to the second configuration includes changing an order of depositing the free layer and the pinned layer.

4. The method of claim 2, wherein adjusting the memory cell from the first configuration to the second configuration includes changing a route of a conductive path between the access transistor and the MTJ structure.

5. The method of claim 1, wherein the switching current ratio is a ratio of a first switching current to switch the MTJ structure from a high-resistance state to a low-resistance state to a second switching current to switch the MTJ structure from the low-resistance state to the high-resistance state.

6. The method of claim 1, further comprising:

determining a switching characteristic of the memory cell; and

performing a transistor loadline analysis to determine the switching current ratio.

7. The method of claim 1, further comprising:

determining an amount to modify the offset magnetic field based on a magnitude of the switching current ratio.

8. The method of claim 7, wherein the amount to modify the offset magnetic field is determined using at least one of a mathematical model and an empirical model of a relationship between the switching current ratio, the offset magnetic field, and a switching field strength.

9. The method of claim 1, wherein modifying the offset magnetic field includes adjusting a thickness of a pinned layer of the MTJ structure.

10. The method of claim 9, further comprising, prior to adjusting the thickness of the pinned layer, determining a predicted thermal stability of the MTJ structure in the presence of the modified offset magnetic field by applying an external magnetic field to the MTJ structure.

11. The method of claim 9, further comprising:

fabricating the memory cell;

measuring a spin torque transfer (STT) switching characteristic of the memory cell;

performing a transistor loadline analysis to determine the switching current ratio;

applying an external magnetic field to simulate operation of the MTJ structure with the adjusted thickness of the pinned layer; and

testing a thermal stability of the memory cell in the presence of the external magnetic field.

12. The method of claim 9, wherein the switching current ratio is less than an unadjusted switching current ratio of the MTJ structure and wherein the pinned layer is a synthetic layer that includes:

a first magnetic layer that is proximate to the free layer; and

a second magnetic layer having a magnetic moment that is antiparallel to a magnetic moment of the first magnetic layer,

wherein adjusting the thickness of the pinned layer includes decreasing a thickness of the second magnetic layer to apply a negative shift to the offset magnetic field.

13. The method of claim 12, wherein the switching current ratio enables switching of the memory cell when the access transistor is in a source loading state.

14. The method of claim 1, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of a pinned layer of the MTJ structure in a first state and antiparallel to the magnetic moment of the pinned layer in a second state, and wherein the switching current ratio is based on a first critical current density to switch from the first state to the second state divided by a second critical current density to switch from the second state to the first state.

15. The method of claim 1, wherein the memory cell is incorporated into a memory of a portable electronic device.

16. The method of claim 1, wherein determining the switching current ratio and modifying the offset magnetic field are performed at a processor integrated into an electronic device.

17. An apparatus comprising a spin torque transfer magnetoresistive random access memory (STT-MRAM) that includes a memory cell that is designed in accordance with the method of claim 1.

18. The apparatus of claim 17, further comprising:

a processor coupled to the STT-MRAM and configured to perform memory operations at the memory cell of the STT-MRAM;

a display device coupled to the processor; and

a speaker coupled to the processor, wherein processor further configured to initiate data presentation via the display device and the speaker.

19. The apparatus of claim 17 integrated in at least one semiconductor die.

20. The apparatus of claim 17, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the STT-MRAM is integrated.

21. A method comprising:

a first step for determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell, the memory cell including the MTJ structure coupled to an access transistor; and

a second step for modifying an offset magnetic field that is incident to a free layer of the MTJ structure, wherein the modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

22. The method of claim 21, wherein the first step and the second step are performed at a processor integrated into an electronic device.

23. An apparatus comprising:

a memory cell comprising;

a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

24. The apparatus of claim 23, wherein the first switching current is less than a first threshold associated with an operating current characteristic of the access transistor, and wherein the operating current characteristic of the access transistor comprises a current from a drain terminal of the access transistor to a source terminal of the access transistor at a predetermined voltage between a gate terminal of the access transistor and the drain terminal of the access transistor.

25. The apparatus of claim 23, wherein the free layer is positioned a first distance from the drain terminal and the pinned layer is positioned a second distance from the drain terminal, the first distance greater than the second distance, and wherein a conductive path electrically connects the drain terminal to the free layer.

26. The apparatus of claim 23, wherein the free layer is positioned a first distance from drain terminal and the pinned layer is positioned a second distance from the drain terminal, the second distance greater than the first distance, and wherein a conductive path electrically connects the drain terminal to the free layer.

27. The apparatus of claim 23 integrated in at least one semiconductor die.

28. The apparatus of claim 23, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the memory cell is integrated.

29. An apparatus comprising:

means for storing a data value as an orientation of a magnetic moment that is programmable by a spin polarized current exceeding a threshold current density, the means for storing the data value coupled to a bit line; and

means for storing a pinned magnetic moment having a pinned orientation, wherein the magnetic moment that is programmable is substantially parallel to the pinned magnetic moment in a first state and substantially antiparallel to the pinned magnetic moment in a second state,

wherein the means for storing the pinned magnetic moment has a physical dimension to produce an offset magnetic field corresponding to a first switching current to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

30. The apparatus of claim 29 integrated in at least one semiconductor die.

31. The apparatus of claim 29, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the means for storing the data value and the means for storing the pinned magnetic moment are integrated.

32. An apparatus comprising:

a memory device comprising;

a plurality of memory cells, wherein at least one memory cell of the plurality of memory cells comprises;

a magnetic tunnel junction (MTJ) structure, wherein a magnetic moment of a free layer of the MTJ structure is substantially parallel to a magnetic moment of a pinned layer of the MTJ structure in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state; and

an access transistor coupled to the MTJ structure,

wherein a ratio of a magnitude of a first switching current to switch the MTJ structure from the first state to the second state is less than half of a second switching current to switch the MTJ structure from the second state to the first state.

33. The apparatus of claim 32 integrated in at least one semiconductor die.

34. The apparatus of claim 32, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the memory device is integrated.

35. A computer readable tangible medium storing instructions executable by a computer, the instructions comprising:

instructions that are executable by the computer to determine a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell, the memory cell including the MTJ structure coupled to an access transistor; and

instructions that are executable by the computer to modify an offset magnetic field that is incident to a free layer of the MTJ structure, wherein the modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

36. The computer readable tangible medium of claim 35, wherein the instructions are executable by a processor integrated in a device selected from the group consisting of a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

37. A method comprising:

receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line;

transforming the design information to comply with a file format; and

generating a data file including the transformed design information.

38. The method of claim 37, wherein the data file includes a GDSII format.

39. A method comprising:

receiving a data file including design information corresponding to a semiconductor device; and

fabricating the semiconductor device according to the design information, wherein the semiconductor device includes a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

40. The method of claim 39, wherein the data file has a GDSII format.

41. A method comprising:

receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line; and

transforming the design information to generate a data file.

42. The method of claim 41, wherein the data file has a GERBER format.

43. A method comprising:

receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and

manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

44. The method of claim 43, wherein the data file has a GERBER format.

45. The method of claim 43, further comprising integrating the circuit board into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.