SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100221892A1
• Filed: 05/12/2010
• Published: 09/02/2010
• Est. Priority Date: 06/09/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: TAKAO, Yukihiro
• Granted Patent: US 8,101,496 B2
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.

Claims

1. A method of manufacturing a semiconductor device, comprising:

bonding a supporting substrate to a first surface of a semiconductor substrate on which a pad electrode is formed;

forming a via hole in the semiconductor substrate connecting a second surface of the semiconductor substrate and a surface of the pad electrode;

forming an insulation film on the second surface of the semiconductor substrate and an inside wall of the via hole;

removing the insulation film at a bottom portion of the via hole to expose the pad electrode;

forming a wiring contacting the exposed pad electrode through the via hole and extending over the second surface from the via hole;

forming a conductive terminal on the wiring; and

dividing the semiconductor substrate into a plurality of semiconductor dice.

2. The method of claim 1, wherein the wiring is formed by electrolytic plating or sputtering.

3. The method of claim 1, further comprising forming a cushioning pad on the insulation film excluding a region adjacent the via hole.

4. The method of claim 1, wherein the following conditions are met:

0.7 Ks≦

Kg≦

1.3 Ks

where Kg denotes a thermal expansion coefficient of the supporting substrate and Ks denotes a thermal expansion coefficient of the semiconductor substrate.

9. The method of claim 1, wherein the supporting substrate is a glass substrate on which no wiring is formed.

10. The method of claim 1, further comprising a resin layer bonding the supporting substrate to a passivation film formed on the pad electrode.

11. The method of claim 1, wherein the wiring completely fills the via hole.

5. A method of manufacturing a semiconductor device, comprising:

bonding a supporting substrate to a first surface of a semiconductor substrate on which a pad electrode is formed;

forming a via hole in the semiconductor substrate connecting a second surface of the semiconductor substrate and a surface of the pad electrode;

forming an insulation film on the second surface of the semiconductor substrate and an inside wall of the via hole;

removing the insulation film at a bottom portion of the via hole to expose the pad electrode;

forming a buried electrode in the via hole so that the buried electrode is in contact with the exposed pad electrode;

forming a cushioning pad on the second surface;

forming a wiring connected with the buried electrode and extending over the cushioning pad;

forming a conductive terminal on the wiring; and

dividing the semiconductor substrate into a plurality of semiconductor dice.

6. The method of claim 5, wherein the buried electrode is formed by electrolytic plating or sputtering.

7. The method of claim 5, wherein the wiring is formed by electrolytic plating or sputtering.

8. The method of claim 5, wherein the following conditions are met:

0.7 Ks≦

Kg≦

1.3 Ks

where Kg denotes a thermal expansion coefficient of the supporting substrate and Ks denotes a thermal expansion coefficient of the semiconductor substrate.

12. The method of claim 5, wherein the supporting substrate is a glass substrate on which no wiring is formed.

13. The method of claim 5, further comprising a resin layer bonding the supporting substrate to a passivation film formed on the pad electrode.

14. The method of claim 5, wherein the wiring completely fills the via hole.