CENTRAL PROCESSING UNIT CAPABLE OF MULTI-BOOT USING DESJOINT MEMORY SPACES
First Claim
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1. A central processing unit comprising:
- a plurality of internal registers communicably coupled to a plurality of disjoint memory spaces, wherein the internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space.
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Abstract
A central processing unit capable of multi-boot using disjoint memory spaces. The central processing unit comprises a plurality of internal registers communicably coupled to each of a plurality of disjoint memory spaces. The internal registers may be configured to designate one or more of the memory spaces as an active memory space or a standby memory space.
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Citations
17 Claims
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1. A central processing unit comprising:
a plurality of internal registers communicably coupled to a plurality of disjoint memory spaces, wherein the internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A central processing unit comprising:
a plurality of internal registers communicably coupled to a plurality of disjoint memory spaces, wherein the internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space, and wherein a memory manager communicably couples the plurality of disjoint memory spaces to the internal registers. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
Specification