CENTRAL PROCESSING UNIT CAPABLE OF MULTI-BOOT USING DESJOINT MEMORY SPACES

• US 20100223452A1
• Filed: 03/01/2010
• Published: 09/02/2010
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: Keicy Chung
• Original Assignee: Keicy Chung
• Inventors: Chung, Keicy
• Granted Patent: US 8,775,780 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 9/441 Multiboot arrangements, i.e. selecting an operating system to be loaded

Abstract

A central processing unit capable of multi-boot using disjoint memory spaces. The central processing unit comprises a plurality of internal registers communicably coupled to each of a plurality of disjoint memory spaces. The internal registers may be configured to designate one or more of the memory spaces as an active memory space or a standby memory space.

Claims

1. A central processing unit comprising:

a plurality of internal registers communicably coupled to a plurality of disjoint memory spaces, wherein the internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space.

2. The central processing unit of claim 1, wherein the internal registers are further configured to prevent machine instructions in the active memory space from accessing the standby memory space.

3. The central processing unit of claim 1, wherein the internal registers are further configured to direct an operating system to boot into the active memory space.

4. The central processing unit of claim 1, wherein the internal registers are further configured to direct an operating system to boot into the inactive memory space during processor idle time with respect to the active memory space.

5. The central processing unit of claim 1, wherein the internal registers are further configured to track machine instruction entry points corresponding to each of the active and standby memory spaces.

6. The central processing unit of claim 1, wherein the internal registers are further configured to switch designations of the active and standby memory spaces.

7. The central processing unit of claim 1, further comprising a memory manager communicably coupling the plurality of disjoint memory spaces to the internal registers.

8. A central processing unit comprising:

a plurality of internal registers communicably coupled to a plurality of disjoint memory spaces, wherein the internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space, and wherein a memory manager communicably couples the plurality of disjoint memory spaces to the internal registers.

9. The central processing unit of claim 8, wherein the internal registers are further configured to prevent machine instructions in the active memory space from accessing the standby memory space.

10. The central processing unit of claim 8, wherein the internal registers are further configured to direct an operating system to boot into the active memory space.

11. The central processing unit of claim 8, wherein the internal registers are further configured to direct an operating system to boot into the standby memory space during processor idle time with respect to the active memory space.

12. The central processing unit of claim 8, wherein the internal registers are further configured to track machine instruction entry points corresponding to each of the active and standby memory spaces.

13. The central processing unit of claim 8, wherein the internal registers are further configured to switch designations of the active and standby memory spaces.

14. The central processing unit of claim 8, wherein the memory manager is configured to convert a plurality of disjoint memory spaces to a single addressable memory space.

15. The central processing unit of claim 8, wherein the memory manager is configured to form a mirrored-pair of memory spaces during the boot process, and to subsequently convert the mirrored-pair of memory spaces to disjoint memory spaces, so that each disjoint memory space is loaded with an operating system.

16. The central processing unit of claim 8, wherein the memory manager is configured to flush the standby memory space before the standby memory space is loaded with an operating system.

17. The central processing unit of claim 8, wherein the memory manager is configured to track defective memory spaces.