COMPACT JTAG ADAPTER

• US 20100223519A1
• Filed: 05/10/2010
• Published: 09/02/2010
• Est. Priority Date: 03/21/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Granted Patent: US 8,136,003 B2
• Time in Patent Office: Days
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Claims

1. A debug and test system adapter comprising:

A. a link interface including;

i. a bidirectional test clock lead; and

ii. a bidirectional test mode select lead; and

B. a second interface including;

i. a first clock in lead;

ii. a test clock lead;

iii. a test mode select lead;

iv. a test data in lead; and

v. a test data out lead.

2. An adapter circuit comprising:

A. first interface leads including;

i. a bidirectional test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces.

3. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a bidirectional test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces.

4. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with link identification bits.

5. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with power control bits.

6. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register having test reset bits for the second and third interfaces bits.

7. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a scan control register with a flatten scan path bit.

8. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with scan format bits.

9. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with delay length bits.

10. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with selection bits.

11. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with a scan status bit.

12. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with background data transport bits.

13. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a control register with a custom data transport bit.

14. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including gating coupling the test clock lead of the first interface and the test clock out leads of the second and third interface leads.

15. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including a bypass register coupled with the test data out leads of the second and third interface leads.

16. An adapter circuit comprising:

A. first interface leads including;

i. a test clock lead; and

ii. a test mode select lead;

B. second interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead;

C. third interface leads including;

i. a test clock out lead;

ii. a test mode select out lead;

iii. a test data in lead; and

iv. a test data out lead; and

D. control circuitry selectively coupling the signals of the first interface with the signals of the second and third interfaces, the control circuitry including reset and escape detection circuitry coupled with the test clock lead and test mode select lead of the first interface.

17. A process of operating a debug and test system, comprising:

A. providing a first set of signals including a test data input signal, a test data output signal, a test clock signal, and a test mode select signal;

B. providing a second set of signals that is different from the first set of signals;

C. serializing the first and second sets of signals into a third set of signals separate from the first and second sets of signals; and

D. multiplexing and demultiplexing one of the first set of signals and the third set of signals with outputs of the debug and test system in response to a mode control signal from format select register circuitry.

18. The process of claim 17 in which the providing a first set of signals includes providing a return test clock signal.

19. The process of claim 17 in which the serializing into a third set of signals includes serializing a TMSC signal.

20. The process of claim 17 in which the multiplexing and demultiplexing includes multiplexing and demultiplexing the first set of signals of a test data input signal, a test data output signal, a test clock signal, and a test mode select signal on the outputs in a first mode, and multiplexing and demultiplexing the third set of signals of a test clock signal and a TMSC signal on the outputs in a second mode.