SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100224873A1
• Filed: 03/04/2010
• Published: 09/09/2010
• Est. Priority Date: 03/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: HIROHASHI, Takuya, SAKATA, Junichiro, KISHIDA, Hideyuki
• Granted Patent: US 8,492,757 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer including a channel formation region over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein in the buffer layer, a first region which is in contact with the source and drain electrode layers has higher electrical conductivity than a second region which is in contact with the channel formation region of the oxide semiconductor layer.

2. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer including a channel formation region over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the buffer layer is an oxide semiconductor layer including a metal selected from group consisting of titanium, molybdenum, manganese and combination thereof, and

wherein in the buffer layer, a first region which is in contact with the source and drain electrode layers has higher electrical conductivity than a second region which is in contact with the channel formation region of the oxide semiconductor layer.

3. The semiconductor device according to claim 2, wherein a concentration of oxygen contained in the first region is lower than a concentration of oxygen contained in the second region.

4. The semiconductor device according to claim 2,

wherein the source and drain electrode layers includes a titanium film, and

wherein the titanium film is in contact with the first region of the oxide semiconductor layer.

5. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer including a channel formation region over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein in the buffer layer, a first region which is in contact with the source and drain electrode layers is a metal region and a second region which is in contact with the channel formation region of the oxide semiconductor layer is a metal oxide region, and

wherein the metal oxide region has lower electrical conductivity than the channel formation region of the oxide semiconductor layer.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer including a channel formation region over the gate insulating layer;

forming a second oxide semiconductor layer including a metal selected from group consisting of titanium, molybdenum, manganese and a combination thereof over the first oxide semiconductor layer; and

forming source and drain electrode layers over the second oxide semiconductor layer,

wherein heat treatment is performed on the second oxide semiconductor layer including a metal selected from group consisting of titanium, molybdenum, manganese and a combination thereof and the source and drain electrode layers, so that in the second oxide semiconductor layer, a first region which is in contact with the source and drain electrode layers has higher electrical conductivity than a second region which is in contact with the channel formation region of the first oxide semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein a concentration of oxygen contained in the first region is made lower than a concentration of oxygen contained in the second region by the heat treatment.

8. The method for manufacturing a semiconductor device according to claim 6,

wherein the source and drain electrode layers are formed using a titanium film, and

wherein the titanium film is formed to be in contact with the first region of the second oxide semiconductor layer.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer including a channel formation region over the gate insulating layer;

forming a metal film over the oxide semiconductor layer; and

forming source and drain electrode layers over a first region of the metal film,

wherein in the metal film, oxidation treatment is performed on a second region which is in contact with the channel formation region of the oxide semiconductor layer, so that a metal oxidation region is formed.

10. The method for manufacturing a semiconductor device according to claim 9, wherein oxygen plasma treatment is performed as the oxidation treatment.