P-CHANNEL SILICON CARBIDE MOSFET

• US 20100224886A1
• Filed: 03/04/2010
• Published: 09/09/2010
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Systems Company Limited
• Inventors: IWAMURO, Noriyuki
• Granted Patent: US 8,198,676 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 μm. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.

Claims

1. A p-channel silicon carbide MOSFET comprising:

a silicon carbide semiconductor substrate;

a high-concentration p-type layer containing silicon carbide semiconductor provided on one principal surface of the silicon carbide semiconductor substrate;

a low-concentration p-type base layer containing silicon carbide semiconductor provided on the high-concentration p-type layer;

an n-type base layer containing silicon carbide semiconductor provided on the low-concentration p-type base layer;

p-type source regions selectively formed on a surface layer of the n-type base layer;

first trenches extending from the p-type source regions, passing through the n-type base layer and reaching the p-type base layer;

control electrodes packed through gate insulating films on surfaces of the p-type base layer exposed from inner surfaces of the first trenches;

second trenches extending from the surface of the n-type base layer, passing through the n-type base layer and reaching the p-type base layer;

source electrodes in contact with inner surfaces of the second trenches while being in contact with the n-type base layer and the p-type source layer as contact regions located in the substrate surface around opening portions of the second trenches; and

a drain electrode in contact with the other principal surface of the silicon carbide semiconductor substrate,

wherein a plane pattern of the first trenches has a wide-interval first trench pattern portion where the second trench and the contact region are disposed between the first trenches, and a narrow-interval first trench pattern portion where the second trench and the contact region are not disposed between the first trenches;

wherein each second trench has a depth not smaller than each first trench;

wherein a distance between center lines of the first trench and the second trench is not larger than 10 μ

m;

wherein each of the source electrodes has a Schottky junction between the source electrode and a surface of the p-type base layer in a bottom portion of the second trench;

wherein third trenches are provided so as to extend from the other principal surface of the silicon carbide semiconductor substrate and reach the high-concentration p-type layer; and

wherein the drain electrode is in contact with p-type layer surface-containing inner surfaces of bottom portions of the third trenches.

2. A p-channel silicon carbide MOSFET comprising:

a silicon carbide semiconductor substrate;

a high-concentration p-type layer containing silicon carbide semiconductor provided on one principal surface of the silicon carbide semiconductor substrate;

a low-concentration p-type base layer containing silicon carbide semiconductor provided on the high-concentration p-type layer;

an n-type base layer containing silicon carbide semiconductor provided on the low-concentration p-type base layer;

p-type source regions selectively formed on a surface layer of the n-type base layer;

first trenches extending from the p-type source regions, passing through the n-type base layer and reaching the p-type base layer;

control electrodes packed through gate insulating films on surfaces of the p-type base layer exposed from inner surfaces of the first trenches;

second trenches extending from the surface of the n-type base layer, passing through the n-type base layer and reaching the p-type base layer;

source electrodes being in contact with inner surfaces of the second trenches while being in contact with the n-type base layer and the p-type source layer as contact regions located in the substrate surface around opening portions of the second trenches; and

a drain electrode being in contact with the other principal surface of the silicon carbide semiconductor substrate;

wherein a plane pattern of the first trenches has a wide-interval first trench pattern portion where the second trench and the contact region are disposed between the first trenches, and a narrow-interval first trench pattern portion where the second trench and the contact region are not disposed between the first trenches;

wherein each second trench has a depth not smaller than each first trench;

wherein a distance between center lines of the first trench and the second trench is not larger than 10 μ

m;

wherein each of the source electrodes has a Schottky junction between the source electrode and a surface of the p-type base layer in a bottom portion of the second trench; and

wherein the silicon carbide semiconductor substrate is of a p type as its conductivity type and has a specific resistance not larger than 0.1 Ω

cm.

3. A method of manufacturing a p-channel silicon carbide MOSFET comprising:

providing a high-concentration p-type layer containing silicon carbide semiconductor on one principal surface of a silicon carbide semiconductor substrate;

providing a low-concentration p-type base layer containing silicon carbide semiconductor provided on the high-concentration p-type layer;

providing an n-type base layer containing silicon carbide semiconductor on the low-concentration p-type base layer;

selectively forming p-type source regions on a surface layer of the n-type base layer;

providing first trenches extending from the p-type source regions, passing through the n-type base layer and reaching the p-type base layer;

providing control electrodes packed through gate insulating films on surfaces of the p-type base layer exposed from inner surfaces of the first trenches;

providing second trenches extending from the surface of the n-type base layer, passing through the n-type base layer and reaching the p-type base layer;

providing third trenches so as to extend from the other principal surface of the silicon carbide semiconductor substrate and reach the high-concentration p-type layer; and

providing source electrodes in contact with inner surfaces of the second trenches while being in contact with the n-type base layer and the p-type source layer as contact regions located in the substrate surface around opening portions of the second trenches; and

providing a drain electrode in contact with the other principal surface of the silicon carbide semiconductor substrate,

wherein a plane pattern of the first trenches has a wide-interval first trench pattern portion where the second trench and the contact region are disposed between the first trenches, and a narrow-interval first trench pattern portion where the second trench and the contact region are not disposed between the first trenches;

wherein each second trench has a depth not smaller than each first trench;

wherein a distance between center lines of the first trench and the second trench is not larger than 10 μ

m;

wherein each of the source electrodes has a Schottky junction between the source electrode and a surface of the p-type base layer in a bottom portion of the second trench; and

wherein the drain electrode is in contact with p-type layer surface-containing inner surfaces of bottom portions of the third trenches.

4. A method of manufacturing a p-channel silicon carbide MOSFET according to claim 3, further comprising grinding the other principal surface of the silicon carbide semiconductor substrate until a desired thickness is reached, wherein, after the other principal surface of the silicon carbide semiconductor substrate is ground, the third trenches are provided to extend from the ground other principal surface and reach the high-concentration p-type layer and the drain electrode is then applied on the other principal surface of the silicon carbide semiconductor substrate so as to come into contact with the high-concentration p-type layer.