SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR MAKING THE SAME

• US 20100224900A1
• Filed: 03/04/2010
• Published: 09/09/2010
• Est. Priority Date: 03/06/2009
• Status: Abandoned Application

• Current Assignee: Advanced Optoelectronic Technology, Inc.
• Original Assignee: Advanced Optoelectronic Technology, Inc.
• Inventors: TU, PO MIN, YEH, YING CHAO, LIN, WEN YU, WU, PENG YI, CHAN, SHIH HSIUNG, HUANG, SHIH CHENG, MA, CHIH PANG
• Application Number:
  US12/717,671
• Publication Number:
  US 20100224900A1
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

A semiconductor optoelectronic device with enhanced light extraction efficiency includes a major luminescent area and a secondary luminescent area, wherein the major luminescent area is surrounded by a secondary luminescent area. The secondary luminescent area not only can improve the light extraction efficiency of the major luminescent area, but per se also can luminesce. In addition, one embodiment of the present invention provides a fabricating method for forming the secondary luminescent area.

Claims

1. A semiconductor optoelectronic device with enhanced light extraction efficiency, comprising:

a substrate;

a first luminescent area; and

a second luminescent area including a plurality of holes surrounding said first luminescent area, each of said first luminescent area and said second luminescent area comprising;

an n-type conduction layer disposed on said substrate;

a luminescent layer formed on said n-type conduction layer;

a p-type conduction layer formed on said luminescent layer; and

a transparent conductive layer disposed on said p-type conduction layer.

2. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 1, further comprising a buffer layer formed between said substrate and said n-type conduction layer.

3. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 2, wherein said buffer layer is gallium nitride, aluminum gallium nitride, aluminum nitride, or In_xGa_1-xN/In_yGa_1-yN while x≠

y.

4. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 1, wherein said transparent conductive layer is nickel gold alloy, indium tin oxide, indium zinc oxide, indium tungsten oxide, or indium gallium oxide.

5. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 1, further comprising a p-type electrode electrically connecting to said p-type conduction layer and a protection layer covering said first luminescent area and said second luminescent area, while exposing said p-type electrode.

6. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 1, further comprising a p-type electrode electrically connecting to said p-type conduction layer, an n-type electrode electrically connecting to said n-type conduction layer and a protection layer covering said first luminescent area and said second luminescent area, while exposing said p-type electrode and said n-type electrode.

7. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 6, wherein said protection layer is silicon oxide or silicon nitride.

8. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 1, wherein said hole has a diameter of from 0.1 to 10 micrometers.

9. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 8, wherein the height of said hole is between the height of said p-type conduction layer and the height of said n-type conduction layer.

10. The semiconductor optoelectronic device with enhanced light extraction efficiency of claim 9, wherein said hole includes a roughened side surface.

11. A method for forming a semiconductor optoelectronic device with enhanced light extraction efficiency, comprising the steps of:

providing a substrate;

forming a luminescent structure on said substrate, said luminescent structure comprising;

an n-type conduction layer formed on said substrate;

a luminescent layer formed on said n-type conduction layer; and

a p-type conduction layer formed on said luminescent layer; and

etching said luminescent structure to form a first luminescent area and a second luminescent area including a plurality of holes surrounding said first luminescent area.

12. The method of claim 11, further comprising a step of forming a buffer layer between said substrate and said n-type conduction layer.

13. The method of claim 12, wherein said buffer layer is gallium nitride, aluminum gallium nitride, aluminum nitride, or In_xGa_1-xN/In_yGa_1-yN while x≠

y.

14. The method of claim 11, wherein said transparent conductive layer is nickel gold alloy, indium tin oxide, indium zinc oxide, indium tungsten oxide, or indium gallium oxide.

15. The method of claim 11, further comprising a step of forming a p-type electrode electrically connecting to said p-type conduction layer and a protection layer covering said first luminescent area and said second luminescent area, while exposing said p-type electrode.

16. The method of claim 11, further comprising a step of forming a p-type electrode electrically connecting to said p-type conduction layer, an n-type electrode electrically connecting to said n-type conduction layer and a protection layer covering said first luminescent area and said second luminescent area, while exposing said p-type electrode and said n-type electrode.

17. The method of claim 16, wherein said protection layer is silicon oxide or silicon nitride.

18. The method of claim 11, wherein said hole has a diameter of from 0.1 to 10 micrometers.

19. The method of claim 18, wherein the height of said hole is between the height of said p-type conduction layer and the height of said n-type conduction layer.

20. The method of claim 19, wherein said hole includes a roughened side surface.