SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20100224909A1
• Filed: 05/19/2010
• Published: 09/09/2010
• Est. Priority Date: 08/29/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Miura, Takashi, OOHARA, Kanji
• Application Number:
  US12/783,135
• Publication Number:
  US 20100224909A1
• Time in Patent Office: Days
• US Class Current: 257/140
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A first well region of a second conductivity type is formed in the portion of the semiconductor layer of the first conductivity type located in an element portion in which a vertical element is disposed, while a second well region of the second conductivity type is formed in the portion of the semiconductor layer located in a peripheral portion surrounding the element portion. A field insulating film is formed on the portion of the semiconductor layer located in a field portion interposed between the element portion and the peripheral portion. A depletion stop region of the first conductivity type having an impurity concentration higher than that of the semiconductor layer is formed in a surface portion of the semiconductor layer located under at least the portion of the field insulating film adjacent to the peripheral portion.

Claims

1. A semiconductor device divided in an element portion in which a vertical element is disposed, a peripheral portion surrounding the element portion, and a field portion interposed between the element portion and the peripheral portion, the semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer of the first conductivity type formed on a top surface of the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate;

a first well region of a second conductivity type formed in a portion of the semiconductor layer located in the element portion;

a second well region of the second conductivity type formed in a portion of the semiconductor layer located in the peripheral portion; and

a field insulating film formed on a portion of the semiconductor layer located in the field portion, wherein

a depletion stop region of the first conductivity type having an impurity concentration higher than that of the semiconductor layer is formed in a surface portion of the semiconductor layer located under at least a portion of the field insulating film adjacent to the peripheral portion.

2. The semiconductor device of claim 1, wherein the depletion stop region is formed so as to extend in the second well region.

3. The semiconductor device of claim 2, wherein

a channel stopper region of the first conductivity type having an impurity concentration higher than that of the depletion stop region is formed in a surface portion of the depletion stop region located in the second well region, and

a first electrode electrically connected to the channel stopper region is formed on the channel stopper region.

4. The semiconductor device of claim 2, wherein a first electrode electrically connected to the depletion stop region is formed on a portion of the depletion stop region located in the second well region.

5. The semiconductor device of claim 3, wherein the first electrode is an EQR electrode.

6. The semiconductor device of claim 1, wherein the depletion stop region includes a plurality of portions separated from each other.

7. The semiconductor device of claim 1, wherein

the first well region is formed to adjoin the field insulating film, and

a second electrode is formed on a portion of the first well region adjacent to the field insulating film with an insulating film interposed therebetween.

8. The semiconductor device of claim 7, wherein the second electrode is formed also on a portion of the field insulating film adjacent to the first well region.

9. The semiconductor device of claim 1, further comprising:

a trench formed so as to extend through the first well region; and

a buried gate electrode formed in the trench with a gate insulating film interposed between the buried gate electrode and the wall surface of the trench.

10. The semiconductor device of claim 9, further comprising:

a source region of the first conductivity type formed in a surface portion of the first well region to adjoin the buried gate electrode.

11. The semiconductor device of claim 10, further comprising:

a body contact region of the second conductivity type formed in a surface portion of the first well region to adjoin each of the buried gate electrode and the source region.

12. The semiconductor device of claim 11, further comprising:

a source electrode formed over the source region and the body contact region so as to electrically connect the source region and the body contact region; and

a drain electrode formed on the back surface of the semiconductor substrate.

13. The semiconductor device of claim 1, wherein the vertical element is a vertical MISFET or a vertical IGBT.

14. A method for fabricating a semiconductor device divided in an element portion in which a vertical element is disposed, a peripheral portion surrounding the element portion, and a field portion interposed between the element portion and the peripheral portion, the method comprising the steps of:

forming, on the top surface of a semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate;

forming a depletion stop region of the first conductivity type having an impurity concentration higher than that of the semiconductor layer in a surface portion of the semiconductor layer located in at least a portion of the field portion adjacent to the peripheral portion;

forming a field insulating film on a portion of the semiconductor layer located in the field portion so as to overlap at least a part of the depletion stop region; and

forming a first well region of a second conductivity type in a portion of the semiconductor layer located in the element portion, while forming a second well region of the second conductivity type in a portion of the semiconductor layer located in the peripheral portion.