METHOD FOR PRODUCING SEMICONDUCTOR CHIP, AND FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME

• US 20100224915A1
• Filed: 01/12/2007
• Published: 09/09/2010
• Est. Priority Date: 01/16/2006
• Status: Active Grant

• Current Assignee: JOLED Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakagawa, Tohru, Kawashima, Takahiro, Saitoh, Tohru, Torii, Hideo
• Granted Patent: US 8,242,025 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing

Abstract

According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).

Claims

1. A method of manufacturing a semiconductor piece, comprising the steps of:

(i) stacking a sacrificial layer and a semiconductor layer on a substrate in this order, and repeating the stacking so as to form the semiconductor layers on the substrate, the number of the semiconductor layers being at least two;

(ii) etching part of the sacrificial layers and part of the semiconductor layers so as to divide the semiconductor layers into pieces; and

(iii) removing the sacrificial layers so as to separate the pieces from the substrate.

2. The manufacturing method according to claim 1,

wherein in the step (iii), the sacrificial layers are removed by wet etching.

3. The manufacturing method according to claim 1, further comprising

a step of lowering the resistance of both ends of the piece before the step (iii).

4. The manufacturing method according to claim 1,

wherein the step (i) is steps of stacking the sacrificial layer, the semiconductor layer, and an insulating layer in this order, and repeating the stacking, and

the step (ii) is a step of etching part of the sacrificial layers, part of the semiconductor layers, and part of the insulating layers so as to divide the semiconductor layers and the insulating layers into pieces.

5. The manufacturing method according to claim 1,

wherein the step (i) is steps of stacking the sacrificial layer, the semiconductor layer, an insulating layer, and a conductive layer in this order, and repeating the stacking, and

the step (ii) is a step of etching part of the sacrificial layers, part of the semiconductor layers, part of the insulating layers, and part of the conductive layers so as to divide the semiconductor layers, the insulating layers and the conductive layers into pieces.

6. The manufacturing method according to claim 1,

wherein the sacrificial layer is made of a crystal.

7. The manufacturing method according to claim 6,

wherein the sacrificial layer is made of SiGe crystal, and

the semiconductor layer is made of crystalline silicon.

8. The manufacturing method according to claim 1,

wherein the sacrificial layer is an organic polymer layer, and

in the step (i), the semiconductor layer is stacked by bonding the semiconductor layer using the organic polymer layer.

9. The manufacturing method according to claim 1,

wherein the semiconductor layer is made of a crystal.

10. The manufacturing method according to claim 1,

wherein the semiconductor layer is made of a single crystal.

11. The manufacturing method according to claim 1, further comprising

a step of dispersing the pieces into a liquid after the step (iii).

17. A method of manufacturing a field-effect transistor, comprising the steps of:

(I) manufacturing a semiconductor piece by the manufacturing method according to claim 1; and

(II) connecting a source electrode and a drain electrode to the semiconductor piece.

12. A field-effect transistor comprising:

a semiconductor piece in which two low-resistance regions are formed and at least a portion of a region sandwiched by the two low-resistance regions serves as a channel region;

a source electrode that is connected to one of the low-resistance regions;

a drain electrode that is connected to the other low-resistance region; and

a gate electrode that is disposed in the vicinity of the semiconductor piece.

13. The field-effect transistor according to claim 12,

wherein an insulating film is formed on one principal surface of the semiconductor piece, the principal surface being located at the side of the gate electrode.

14. The field-effect transistor according to claim 12,

wherein the low-resistance regions are doped with an impurity with a concentration of at least 1×

10¹⁸ atoms/cm³.

15. The field-effect transistor according to claim 12,

wherein a region made of an alloy of a metal and a semiconductor that forms the semiconductor piece exists in the low-resistance regions.

16. The field-effect transistor according to claim 12,

wherein the semiconductor piece is made of silicon.