SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20100224936A1
• Filed: 01/06/2010
• Published: 09/09/2010
• Est. Priority Date: 03/03/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hokazono, Akira
• Application Number:
  US12/683,037
• Publication Number:
  US 20100224936A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects

Abstract

A semiconductor device according to one embodiment includes: adjacent first and second transistors each formed on a semiconductor substrate, the first and second transistors respectively having first and second gate electrodes and sharing a source/drain region therebetween; a first insulating film formed on the first gate electrode; a second insulating film formed on the second gate electrode and comprising a region thicker than the first insulating film; and a self-aligned contact plug connected to the source/drain region, a horizontal distance from a center position of the self-aligned contact plug to the second gate electrode being less than a horizontal distance from a center position between the first and second gate electrodes to the second gate electrode.

Claims

1. A semiconductor device, comprising:

adjacent first and second transistors each formed on a semiconductor substrate, the first and second transistors respectively having first and second gate electrodes and sharing a source/drain region therebetween;

a first insulating film formed on the first gate electrode;

a second insulating film formed on the second gate electrode and comprising a region thicker than the first insulating film; and

a self-aligned contact plug connected to the source/drain region, a horizontal distance from a center position of the self-aligned contact plug to the second gate electrode being less than a horizontal distance from a center position between the first and second gate electrodes to the second gate electrode.

2. The semiconductor device according to claim 1, wherein the self-aligned contact plug is a lower portion of a local interconnect, a portion thereof is located on the second gate electrode via the second insulating film, and an upper portion of the local interconnect is formed on a region in the lower portion located above the second gate electrode.

3. The semiconductor device according to claim 2, further comprising:

a liner film comprising the same material as the first insulating film, having the substantially same thickness as the first insulating film, and covering surfaces of the first and second transistors.

4. The semiconductor device according to claim 3, wherein the self-aligned contact plug is not in contact with a portion of the first insulating film located just above the first gate electrode.

5. The semiconductor device according to claim 2, wherein the self-aligned contact plug is not in contact with a portion of the first insulating film located just above the first gate electrode.

6. The semiconductor device according to claim 1, further comprising:

a liner film comprising the same material as the first insulating film, having the substantially same thickness as the first insulating film, and covering surfaces of the first and second transistors.

7. The semiconductor device according to claim 6, wherein the self-aligned contact plug is not in contact with a portion of the first insulating film located just above the first gate electrode.

8. The semiconductor device according to claim 1, wherein the self-aligned contact plug is not in contact with a portion of the first insulating film located just above the first gate electrode.

9. A semiconductor device, comprising:

adjacent first and second transistors each formed on a semiconductor substrate, the first and second transistors respectively having first and second gate electrodes and sharing a source/drain region therebetween;

a self-aligned contact plug connected to the source/drain region; and

first and second insulating films respectively formed on the first and second gate electrodes, the first and second insulating films each having a sidewall shape in which a thickness on the self-aligned contact plug side is thicker than that on the opposite side, and the first and second insulating films sandwiching the self-aligned contact plug.

10. The semiconductor device according to claim 9, wherein the self-aligned contact plug is a lower portion of a local interconnect, a portion thereof is located on the second gate electrode via the second insulating film, and an upper portion of the local interconnect is formed on a region in the lower portion located above the second gate electrode.

11. The semiconductor device according to claim 10, further comprising:

a third transistor formed on the semiconductor substrate and having a third gate electrode, a space between the third transistor and another adjacent transistor being larger than that between the first and second transistors;

a third insulating film formed on the third gate electrode and being thinner than the first and second insulating films; and

a gate contact plug connected to an upper surface of the third gate electrode.

12. The semiconductor device according to claim 11, further comprising:

a liner film comprising the same material as the third insulating film, having the substantially same thickness as the third insulating film, and covering surfaces of the first, second and third transistors.

13. The semiconductor device according to claim 10, wherein the first insulating film has a width larger than that of the first gate electrode, and the second insulating film has a width larger than that of the second gate electrode.

14. The semiconductor device according to claim 9, further comprising:

a third transistor formed on the semiconductor substrate and having a third gate electrode, a space between the third transistor and another adjacent transistor being larger than that between the first and second transistors;

a third insulating film formed on the third gate electrode and being thinner than the first and second insulating films; and

a gate contact plug connected to an upper surface of the third gate electrode.

15. The semiconductor device according to claim 14, further comprising:

a liner film comprising the same material as the third insulating film, having the substantially same thickness as the third insulating film, and covering surfaces of the first, second and third transistors.

16. The semiconductor device according to claim 9, wherein the first insulating film has a width larger than that of the first gate electrode, and the second insulating film has a width larger than that of the second gate electrode.

17. A method of fabricating a semiconductor device, comprising:

forming adjacent first and second transistors on a semiconductor substrate, the first and second transistors respectively having first and second gate electrodes and sharing a source/drain region therebetween;

forming a first interlayer insulating film between the first and second gate electrodes;

forming a core above the first interlayer insulating film;

forming sidewall insulating films on both sides of the core so as to cover the first and second gate electrodes;

forming a second interlayer insulating film on the first interlayer insulating film and the sidewall insulating films;

forming a contact hole in the first and second interlayer insulating films so as to pass between the sidewall insulating film on the first gate electrode and that on the second gate electrode and reach the source/drain region; and

forming a self-aligned contact plug in the contact hole.

18. The method of fabricating a semiconductor device according to claim 17, wherein the self-aligned contact plug is a lower portion of a local interconnect;

and

an upper portion of the local interconnect is formed on an upper surface of the self-aligned contact plug.

19. The method of fabricating a semiconductor device according to claim 18, wherein the first insulating film has a width larger than that of the first gate electrode, and the second insulating film has a width larger than that of the second gate electrode.

20. The method of fabricating a semiconductor device according to claim 17, wherein the first insulating film has a width larger than that of the first gate electrode, and the second insulating film has a width larger than that of the second gate electrode.