Stress Barrier Structures for Semiconductor Chips

• US 20100224966A1
• Filed: 01/07/2010
• Published: 09/09/2010
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa
• Granted Patent: US 8,643,149 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a layer of low dielectric constant (low-k) insulating layer;

a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry; and

a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer.

2. The semiconductor chip of claim 1, wherein the first stress barrier structure comprises a plurality of interlinked metal lines.

3. The semiconductor chip of claim 1, further comprising a through substrate via passing through at least a portion of the semiconductor substrate, wherein the first metal bump is electrically coupled to the through substrate via.

4. The semiconductor chip of claim 1, further comprising a passivation layer overlying the interconnect metallization structure, wherein the first stress barrier structure is disposed within a passivation layer.

5. The semiconductor chip of claim 1, further comprising a redistribution metal line layer overlying the interconnect metallization structure, wherein the first stress barrier structure is disposed within the redistribution metal line layer.

6. The semiconductor chip of claim 1, wherein the interconnect metallization structure comprises a plurality of metal line levels, and the first stress barrier structure is disposed within a top metal line level of the interconnect metallization structure.

7. The semiconductor chip of claim 1, further comprising a second insulating layer with a higher dielectric constant than the low-k insulating layer in the interconnect metallization structure, wherein the first stress barrier structure is disposed in the second insulating layer.

8. The semiconductor chip of claim 1, further comprising:

a second metal bump disposed over the semiconductor substrate, the second metal bump not coupled to the active circuitry; and

a second stress barrier structure disposed under the second metal bump, and disposed over the low-k insulating layer.

9. The semiconductor chip of claim 8, wherein the first and the second stress barrier structures are disposed in a same insulating layer, and wherein the first and the second stress barrier structures comprise a plurality of interlinked metal lines.

10. A structure comprising:

a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a low-k insulating layer;

a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry;

a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer; and

a substrate disposed over and electrically coupled to the first metal bump, wherein the material of the substrate has a coefficient of thermal expansion different from the semiconductor substrate.

11. The structure of claim 10, wherein the substrate comprises a printed circuit board.

12. The structure of claim 10, further comprising a through substrate via passing through at least a portion of the semiconductor substrate, wherein the first metal bump is electrically coupled to the through substrate via.

13. The structure of claim 10, further comprising a passivation layer overlying the interconnect metallization structure, wherein the first stress barrier structure is disposed within the passivation layer.

14. The structure of claim 10, further comprising a redistribution metal line layer overlying the interconnect metallization structure, wherein the first stress barrier structure is disposed within the redistribution metal line layer.

15. The structure of claim 10, further comprising a second insulating layer with a higher dielectric constant than the low-k insulating layer in the interconnect metallization structure, wherein the first stress barrier structure is disposed in the second insulating layer.

16. The structure of claim 10, further comprising:

a second metal bump disposed over the semiconductor substrate, the second metal bump not coupled to the active circuitry; and

a second stress barrier structure disposed under the second metal bump, and disposed over the low-k insulating layer.

17. The structure of claim 16, wherein the first and the second stress barrier structures are disposed in a same insulating layer, and wherein the first and the second stress barrier structures comprise a plurality of interlinked metal lines.

18. A semiconductor chip comprising:

a semiconductor substrate;

a plurality of insulating layers overlying the semiconductor substrate, wherein at least one of the plurality of the insulating layers is a low-k insulating layer;

a plurality of metal line levels formed in the plurality of insulating layers;

a conductive via passing through the plurality of insulating layers and extending to a portion of the semiconductor substrate;

a metal bump disposed over the plurality of insulating layers and coupled to the conductive via; and

a stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer.

19. The semiconductor chip of claim 18, further comprising a redistribution metal line layer overlying the conductive via, wherein the stress barrier structure is disposed within the redistribution metal line layer, and wherein the conductive via comprises copper.

20. The semiconductor chip of claim 18, further comprising an under bump metal structure disposed over the redistribution metal line and under the metal bump.