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Stress Barrier Structures for Semiconductor Chips

  • US 20100224966A1
  • Filed: 01/07/2010
  • Published: 09/09/2010
  • Est. Priority Date: 03/03/2009
  • Status: Active Grant
First Claim
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1. A semiconductor chip comprising:

  • a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a layer of low dielectric constant (low-k) insulating layer;

    a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry; and

    a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer.

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