Stress Barrier Structures for Semiconductor Chips
First Claim
1. A semiconductor chip comprising:
- a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a layer of low dielectric constant (low-k) insulating layer;
a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry; and
a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer.
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Accused Products
Abstract
Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.
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Citations
20 Claims
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1. A semiconductor chip comprising:
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a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a layer of low dielectric constant (low-k) insulating layer; a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry; and a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A structure comprising:
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a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a low-k insulating layer; a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry; a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer; and a substrate disposed over and electrically coupled to the first metal bump, wherein the material of the substrate has a coefficient of thermal expansion different from the semiconductor substrate. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A semiconductor chip comprising:
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a semiconductor substrate; a plurality of insulating layers overlying the semiconductor substrate, wherein at least one of the plurality of the insulating layers is a low-k insulating layer; a plurality of metal line levels formed in the plurality of insulating layers; a conductive via passing through the plurality of insulating layers and extending to a portion of the semiconductor substrate; a metal bump disposed over the plurality of insulating layers and coupled to the conductive via; and a stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer. - View Dependent Claims (19, 20)
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Specification