Continuity testing apparatus and continuity testing method including open/short detection circuit

• US 20100225331A1
• Filed: 03/04/2010
• Published: 09/09/2010
• Est. Priority Date: 03/09/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Fuchigami, Hiroyuki, Satou, Shouichirou
• Granted Patent: US 8,310,246 B2
• Time in Patent Office: Days
• US Class Current: 324/551
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence

Abstract

A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage.

Claims

1. A continuity testing apparatus for testing a condition of continuity between a semiconductor device and a mounting substrate on which the semiconductor device is mounted, the apparatus comprising:

an open/short detection circuit provided for each of to-be-tested terminals, and configured to determine presence or absence of at least any one of an open-circuit failure and a short-circuit failure in the to-be-tested terminal,

wherein a detected result of the open/short detection circuit is generated based on a condition of continuity of the to-be-tested terminal connected to the open/short detection circuit and a detected result from an open/short detection circuit in a preceding stage, and the generated detected result is outputted to an open/short detection circuit in a succeeding stage, and the condition of continuity is determined based on an output from an open/short detection circuit in a last stage.

2. The continuity testing apparatus according to claim 1, wherein:

when three consecutive open/short detection circuits of the open/short detection circuits are denoted by a first open/short detection circuit, a second open/short detection circuit, and a third open/short detection circuit, respectively,

a detected result of the second open/short detection circuit is generated based on the condition of continuity of the to-be-tested terminal connected to the second open/short detection circuit and a detected result from the first open/short detection circuit, and a detected result of the second open/short detection circuit is outputted to the third open/short detection circuit, and the condition of continuity is determined based on an output from the open/short detection circuit in the last stage.

3. The continuity testing apparatus according to claim 1, wherein:

if the condition of continuity of the to-be-tested terminal connected to the open/short detection circuit comprises any one of the open-circuit failure and the short-circuit failure, then the open/short detection circuit outputs the detected result of the condition of continuity to the open/short detection circuit in the succeeding stage.

4. The continuity testing apparatus according to claim 1, wherein:

if the condition of continuity of the to-be-tested terminal connected to the open/short detection circuit is normal, then the open/short detection circuit outputs an output result of the open/short detection circuit in the preceding stage to the open/short detection circuit in the succeeding stage.

5. The continuity testing apparatus according to claim 1, wherein the open/short detection circuits are connected in a daisy chain.

6. The continuity testing apparatus according to claim 1, wherein the open/short detection circuits each include first and second mode terminals that switch from one to another of a normal operation mode, a detection mode for an open-circuit failure, and a detection mode for a short-circuit failure.

7. The continuity testing apparatus according to claim 6, wherein the open/short detection circuits each include a TDI terminal to which a signal at a same level as the to-be-tested terminal is inputted for detection of an open-circuit failure.

8. The continuity testing apparatus according to claim 7, wherein:

when the first mode terminal is set to a Hi level while the second mode terminal is set to a Lo level, the open/short detection circuit enters a detection mode for an open-circuit failure, and

when all of the to-be-tested terminals are set to a Lo level and the TDI terminal is set to a Lo level, the open/short detection circuit determines a condition of continuity as normal if the output from the open/short detection circuit in the last stage is a Hi level, or determines the presence of an open-circuit failure fixed to a Hi level if the output is a Lo level.

9. The continuity testing apparatus according to claim 7, wherein:

when the first mode terminal is set to a Hi level while the second mode terminal is set to a Lo level, the open/short detection circuit enters a detection mode for an open-circuit failure, and

when all of the to-be-tested terminals are set to a Hi level and the TDI terminal is set to a Hi level, the open/short detection circuit determines a condition of continuity as normal if the output from the open/short detection circuit in the last stage is a Hi level, or determines the presence of an open-circuit failure fixed to a Lo level, if the output is a Lo level.

10. The continuity testing apparatus according to claim 7, wherein:

when the first mode terminal is set to a Lo level while the second mode terminal is set to a Hi level, the open/short detection circuit enters a detection mode for a short-circuit failure, and

when, out of the to-be-tested terminals, odd-numbered terminals are set to a Lo level while even-numbered terminals are set to a Hi level, the open/short detection circuit determines a condition of continuity as normal if the output from the open/short detection circuit in the last stage is a Hi level, or determines the presence of a short-circuit failure if the output is a Lo level.

11. The continuity testing apparatus according to claim 7, wherein:

when the first mode terminal is set to a Lo level while the second mode terminal is set to a Hi level, the open/short detection circuit enters a detection mode for a short-circuit failure, and

when, out of the to-be-tested terminals, odd-numbered terminals are set to a Hi level while even-numbered terminals are set to a Lo level, the open/short detection circuit determines a condition of continuity as normal if the output from the open/short detection circuit in the last stage is a Hi level, or determines the presence of a short-circuit failure if the output is a Lo level.

12. A continuity testing method for testing a condition of continuity between a semiconductor device and a mounting substrate on which the semiconductor device is mounted, the method using an open/short detection circuit provided for each of to-be-tested terminals and configured to determine presence or absence of at least any one of an open-circuit failure and a short-circuit failure in the to-be-tested terminal, the method comprising:

generating a detected result of the open/short detection circuit based on a condition of continuity of the to-be-tested terminal connected to the open/short detection circuit and a detected result from an open/short detection circuit in a preceding stage, and outputting the generated detected result to an open/short detection circuit in a succeeding stage; and

determining the condition of continuity based on an output from an open/short detection circuit in a last stage.

13. The continuity testing method according to claim 12, wherein:

if the condition of continuity of the to-be-tested terminal connected to the open/short detection circuit comprises any one of an open-circuit failure and a short-circuit failure, a detected result of the condition of continuity is outputted to the open/short detection circuit in the succeeding stage.

14. The continuity testing method according to claim 12, wherein:

if the condition of continuity of the to-be-tested terminal connected to the open/short detection circuit is normal, an output result of the open/short detection circuit in the preceding stage is outputted to the open/short detection circuit in the succeeding stage.

15. A continuity testing apparatus, comprising:

a first terminal which transfers a first data to an internal circuit;

a second terminal which transfers a second data to the internal circuit;

a data-in terminal which receives a data-in signal;

a first open detection circuit which is responsive to a first mode signal, the data-in signal, the first data, a first power source potential and a second power source potential, to output first and second control signals;

a second open detection circuit which is responsive to the first mode signal, the data-in signal, the second data, a third control signal corresponding to the first control signal, and a fourth control signal corresponding to the second control signal;

a first gate which is responsive to the first mode signal to transfer the third control signal;

a second gate which is responsive to the first mode signal to transfer the fourth control signal;

a first inverter which receives the third control signal output from the first gate to produce an inverted third control signal;

a first short detection circuit which is responsive to a second mode signal, the first data, and the first and second power source potentials, to output fifth to seventh control signals;

a second short detection circuit which is responsive to the second mode signal, the second data, and eighth to tenth control signals corresponding to the fifth to seventh control signals, respectively, to output an eleventh control signal;

a third gate which is responsive to the second mode signal to transfer the eleventh control signal;

a second inverter which receives the eleventh control signal output from the third gate to produce an inverted eleventh control signal; and

a data-out terminal which receives the inverted third control signal, the fourth control signal and the inverted eleventh control signal.