METHOD AND SYSTEM FOR POWER COMBINING IN A MULTI-PORT DISTRIBUTED ANTENNA

• US 20100225556A1
• Filed: 03/03/2009
• Published: 09/09/2010
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Rofougaran, Ahmadreza
• Granted Patent: US 8,155,601 B2
• Time in Patent Office: Days
• US Class Current: 343/860
• CPC Class Codes: H01Q 3/30 varying the relative phase between the radiating elements of an array H01Q3/2605, H01Q3/2658, H01Q3/2682, H01Q3/44 take precedence
• CPC Class Codes: H01Q 3/34 by electrical means active lenses or reflecting arrays H01Q3/46
• CPC Class Codes: H04B 1/40 Circuits

Abstract

Methods and systems for power combining in a multi-port distributed antenna are disclosed and may include power combining signals from power amplifiers (PAs) on a chip. The PAs may be coupled to a single distributed antenna via antenna ports. A phase of each of the signals may be matched at the antenna ports via phase-matching circuitry. A characteristic impedance may be configured at the ports based on a location of the ports. The PAs may be impedance matched to the antenna ports via impedance matching elements. A power level of the power-combined signals may be monitored via a power detector coupled to the distributed antenna. The power detector may include an envelope detector, such as a diode. The antenna may be integrated on the chip or may be located external to the chip. The signals may include RF signals and the antenna may include a microstrip antenna.

Claims

1. A method for enabling communication, the method comprising:

power combining, within a chip, signals from a plurality of power amplifiers (PAs) on said chip, wherein said PAs are coupled to a single distributed antenna via a plurality of antenna ports; and

matching a phase of each of said signals at said plurality of antenna ports.

2. The method according to claim 1, comprising configuring a characteristic impedance at each of said plurality of antenna ports based on a location of each of said antenna ports.

3. The method according to claim 2, comprising impedance matching said on-chip PAs to said plurality of antenna ports via one or more impedance matching elements.

4. The method according to claim 1, comprising monitoring a power level of said power-combined signals via a power detector coupled to said distributed antenna.

5. The method according to claim 4, wherein said power detector comprises an envelope detector.

6. The method according to claim 5, wherein said envelope detector comprises a diode.

7. The method according to claim 1, wherein said distributed antenna is integrated on said chip.

8. The method according to claim 1, wherein said distributed antenna is located external to said chip.

9. The method according to claim 1, wherein said signals comprise RF signals.

10. The method according to claim 1, wherein said distributed antenna comprises a microstrip antenna.

11. A system for enabling communication, the system comprising:

one or more circuits for use in a wireless device, said one or more circuits comprising a plurality of power amplifiers (PAs) on a chip, and said plurality of on-chip power amplifiers are coupled to a single distributed antenna via a plurality of antenna ports, wherein;

said one or more circuits are operable to power combine signals from said plurality of power amplifiers (PAs); and

said one or more circuits are operable to match a phase of each of said power combined signals at said plurality of antenna ports.

12. The system according to claim 11, wherein said one or more circuits are operable to configure a characteristic impedance at each of said plurality of antenna ports based on a location of each of said antenna ports.

13. The system according to claim 12, wherein said one or more circuits comprise one or more impedance matching elements, which are operable to impedance match said PAs to said plurality of antenna ports via impedance matching elements.

14. The system according to claim 11, wherein said one or more circuits comprise a power detector coupled to said distributed antenna, and said power detector is operable to monitor a power level of said power-combined signals.

15. The system according to claim 14, wherein said one or more circuits comprise an envelope detector, and said envelope detector is operable to function as said power detector.

16. The system according to claim 15, wherein said one or more circuits comprise a diode, and said diode is operable to function as said envelope detector.

17. The system according to claim 11, wherein said distributed antenna is integrated on said chip.

18. The system according to claim 11, wherein said distributed antenna is located external to said chip.

19. The system according to claim 11, wherein said signals comprise RF signals.

20. The system according to claim 11, wherein said distributed antenna comprises a microstrip antenna.