LIQUID CRYSTAL DISPLAY AND FABRICATING METHOD THEREOF

• US 20100225869A1
• Filed: 05/21/2010
• Published: 09/09/2010
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: AHN, Byung Chul, Nam, Seung Hee, Kwon, Oh Nam, Chang, Youn Gyoung, Yoo, Soon Sung, Cho, Heung Lyul
• Granted Patent: US 7,889,304 B2
• Time in Patent Office: Days
• US Class Current: 349/147
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes

Abstract

A liquid crystal display device and a fabricating method thereof for simplifying a process are disclosed. In the method of fabricating the liquid crystal display device, a first conductive pattern group including a gate line and a gate electrode, a common line and a common electrode, a pixel electrode and a pad is formed on a substrate. An insulating film including a plurality of contact holes and a semiconductor pattern is formed on the first mask pattern group. And a second conductive pattern group including a data line, a source electrode and a drain electrode is formed on an insulating film provided with the semiconductor pattern, and exposes an active layer of the semiconductor pattern

Claims

1. A liquid crystal display device, comprising:

a data line crossing a gate line on a substrate to define a pixel area;

an insulating film between the gate line and the data line;

a thin film transistor having a gate electrode, a drain electrode, and a source electrode, and connected to the gate line and the data line;

a plurality of pixel electrodes connected to the thin film transistor in the pixel area;

a plurality of common electrodes substantially parallel to the pixel electrodes in the pixel area;

a common line connected to the common electrodes; and

a pad connected to at least one of the gate line, the data line and the common line;

wherein the gate line, the gate electrode, the pixel electrodes, the common electrodes, the common line, and the pad include a transparent conductive layer,

wherein at least a first of the common electrodes has a multiple-layer structure having a transparent conductive layer and a substantially opaque conductive layer.

2. The device of claim 1, wherein the gate line, the gate electrode and the common line have a multiple-layer structure including the transparent conductive layer and a substantially opaque conductive layer.

3. The device of claim 1, wherein at least a first of the common electrodes has a multiple-layer structure having the transparent conductive layer and a substantially opaque conductive layer, and at least a second of the common electrodes includes the transparent conductive layer.

4. The device of claim 1, wherein an outermost one of the common electrodes in the pixel area has a multiple layer structure having the transparent conductive layer and a substantially opaque conductive layer.

5. The device of claim 1, wherein the gate line, the gate electrode, the common line, at least one of the common electrodes, at least one of the pixel electrodes and the pad have a multiple-layer structure including the transparent conductive layer and a substantially opaque conductive layer.

6. The device of claim 5, wherein the transparent conductive layer extends beyond an edge of the substantially opaque conductive layer.

7. The device of claim 6, wherein the transparent conductive layer of the pad is exposed through a contact hole passing through the substantially opaque conductive layer.

8. The device of claim 1, further comprising:

a storage capacitor provided such that a pixel connecting line extending from the drain electrode of the thin film transistor overlaps with a portion of the common line with the insulating film therebetween.

9. The device of claim 8, further comprising:

a storage capacitor provided such that an upper storage electrode connected to at least one of the pixel electrodes overlaps with a portion of the gate line with the insulating film therebetween.

10. The device of claim 9, wherein the drain electrode and the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

11. The device of claim 1, further comprising:

a storage capacitor provided such that an upper storage electrode connected to at least one of the pixel electrodes overlaps with a portion of the gate line with the insulating film therebetween.

12. The device of claim 11, wherein the drain electrode and the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

13. The device of claim 1, wherein a surface of a channel exposed between the source electrode and the drain electrode of the thin film transistor is oxidized.

14. The device of claim 1, wherein the thin film transistor and the data line are covered by an alignment film.

15. The device of claim 5, further comprising:

a second insulating film on the multiple-layer structure including the transparent conductive layer of the gate line, the gate electrode, the at least one pixel electrode, the at least one common electrode, the common line and the pad.

16. The device of claim 1, wherein the data line is connected to the pad via a contact hole passing through the insulating film.

17-42. -42. (canceled)