Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations

• US 20100226176A1
• Filed: 05/18/2010
• Published: 09/09/2010
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan
• Granted Patent: US 8,036,041 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.

Claims

1. A method of reading a non-volatile memory having addressable pages of memory cells on associated wordlines, each memory cell storing two bits of data, said method comprising:

sensing in an operating cycle the two bits of data together from each addressable page of memory to obtain two binary pages of data;

latching the two binary pages of data separately;

outputting a latched binary page of data every operating cycle except the first two cycles; and

wherein said sensing and latching are performed every two operating cycles during said outputting of a latched binary page from a previous operating cycle.

2. The method of claim 1, wherein said sensing and latching are managed by an operation queue manager.

3. The method of claim 1, further comprising:

providing a state machine; and

wherein said operation queue manager is implemented as a module in the state machine.

4. The method of claim 1, wherein the non-volatile memory cells are flash EEPROM.

5. The method of claim 1, wherein the non-volatile memory cells each has a charge storage element.

6. The method of claim 5, wherein the charge storage element is a dielectric layer.

7. The method of claim 1, wherein the non-volatile memory cells are organized in a NAND architecture.

8. A non-volatile memory having addressable pages of memory cells on associated wordlines, comprising:

means for sensing a group of two binary pages together and latching the two binary pages separately;

means for outputting a latched binary page of data every operating cycle except the first two cycles; and

wherein said means for sensing and latching is active every two operating cycles while said means for outputting of a latched binary page is also active.

9. The method of claim 8, wherein said sensing and latching are managed by an operation queue manager.

10. The non-volatile memory of claim 8, further comprising:

providing a state machine; and

wherein said operation queue manager is implemented as a module in the state machine.

11. The non-volatile memory of claim 8, wherein the non-volatile memory cells are flash EEPROM.

12. The non-volatile memory of claim 8, wherein the non-volatile memory cells each has a charge storage element.

13. The non-volatile memory of claim 12, wherein the charge storage element is a dielectric layer.

14. The non-volatile memory of claim 8, wherein the non-volatile memory cells are organized in a NAND architecture.