PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
First Claim
1. A method for wear leveling control when modifying data in a sub-block of a memory block, comprising:
- programming modified data to an empty sub-block of a new memory block;
erasing the sub-block of the memory block.
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Accused Products
Abstract
A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.
443 Citations
9 Claims
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1. A method for wear leveling control when modifying data in a sub-block of a memory block, comprising:
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programming modified data to an empty sub-block of a new memory block; erasing the sub-block of the memory block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification