×

PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY

  • US 20100226183A1
  • Filed: 05/21/2010
  • Published: 09/09/2010
  • Est. Priority Date: 03/07/2007
  • Status: Active Grant
First Claim
Patent Images

1. A method for wear leveling control when modifying data in a sub-block of a memory block, comprising:

  • programming modified data to an empty sub-block of a new memory block;

    erasing the sub-block of the memory block.

View all claims
  • 11 Assignments
Timeline View
Assignment View
    ×
    ×