APPARATUS AND METHOD FOR BLOCK-BASED DATA STRIPING TO SOLID-STATE MEMORY MODULES WITH OPTIONAL DATA FORMAT PROTOCOL TRANSLATION

• US 20100228885A1
• Filed: 02/09/2010
• Published: 09/09/2010
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Ryan Cartland Mcdaniel
• Original Assignee: Ryan Cartland Mcdaniel
• Inventors: McDaniel, Ryan Cartland
• Granted Patent: US 8,156,252 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Claims

1. An apparatus, comprising:

an SATA to ATA bridge;

an ATA to USB bridge coupled to the SATA to ATA bridge;

a USB interface coupled to the ATA to USB bridge;

a block data striper coupled to the ATA to USB bridge and the USB interface;

a first FLASH memory controller coupled to the USB interface;

a first FLASH memory module coupled to the first FLASH memory controller;

a second FLASH memory controller coupled to the USB interface; and

a second FLASH memory module coupled to the second FLASH memory controller.

2. The apparatus of claim 1, further comprising:

a buffer coupled to the ATA to USB bridge.

3. The apparatus of claim 2, further comprising:

a third FLASH memory controller coupled to the USB interface;

a third FLASH memory module coupled to the third FLASH memory controller;

a fourth FLASH memory controller coupled to the USB interface;

a fourth FLASH memory module coupled to the fourth FLASH memory controller.

a fifth FLASH memory module coupled to the first FLASH memory controller;

a sixth FLASH memory module coupled to the second FLASH memory controller;

a seventh FLASH memory module coupled to the third FLASH memory controller; and

an eighth FLASH memory module coupled to the fourth FLASH memory controller.

wherein the ATA to USB interface, the block data striper, and the buffer are implemented as an FPGA;

a drive identifier EEPROM coupled to the FPGA; and

means for identifying the apparatus electronically.

9. The apparatus of claim 3, further comprising:

a connector coupled to the FPGA;

a separate daughter board, the daughter board including;

a mating connector coupled to the connector;

a fifth FLASH memory controller coupled to the mating connector;

a ninth FLASH memory module coupled to the fifth FLASH memory controller;

a sixth FLASH memory controller coupled to the mating connector; and

a tenth FLASH memory module coupled to the sixth FLASH memory controller.

10. The apparatus of claim 9, wherein the daughter board further includes:

an eleventh FLASH memory module coupled to the fifth FLASH memory controller;

a twelfth FLASH memory module coupled to the sixth FLASH memory controller;

a seventh FLASH memory controller coupled to the mating connector;

a thirteenth FLASH memory module coupled to the seventh FLASH memory controller;

a fourteenth FLASH memory module coupled to the seventh FLASH memory controller;

an eighth FLASH memory controller coupled to the mating connector;

a fifteenth FLASH memory module coupled to the eighth FLASH memory controller; and

a sixteenth FLASH memory module coupled to the eighth FLASH memory controller.

11. The apparatus of claim 10, wherein the daughter board further includes:

a USB interface coupled to the mating connector, the USB interface coupled between the mating connector and the fifth FLASH memory controller, the sixth FLASH memory controller, the seventh FLASH memory controller and the eighth FLASH memory controller.

4. (canceled)

5. (canceled)

6. (canceled)

7. (canceled)

8. (canceled)

12. (canceled)

13. A method, comprising:

receiving data via an SATA bus;

translating the data into ATA format;

separating the data into blocks;

packaging the data in blocks for USB transmission;

transferring the data in blocks in USB format; and

storing the data in blocks in a set of FLASH memory modules.

14. The method of claim 13, further comprising:

buffering the data.

15. The method of claim 14, further comprising:

receiving a data request in SATA format;

translating the request into ATA format;

translating the request into USB format;

relaying the request to the set of FLASH memory modules based on locations of blocks of data of the request;

retrieving corresponding data from the set of FLASH memory modules;

transferring the corresponding data in USB format;

transforming the corresponding data to ATA format;

transforming the corresponding data to SATA format; and

transferring the corresponding data as a response to the request.

16. The method of claim 15, further comprising:

providing a drive identification responsive to a request.

17. A method, comprising:

receiving a data request in SATA format;

translating the request into USB format;

relaying the request to memory based on block locations of the request;

retrieving corresponding data from memory;

transferring the corresponding data in USB format;

transforming the corresponding data to SATA format; and

transferring the corresponding data as a response to the request.

18. (canceled)

19. (canceled)

20. (canceled)

21. An apparatus comprising:

an interface configured to receive data for writing data to a storage system or for reading data from the storage system, the storage system having a plurality of memory modules;

a plurality of memory controllers each coupled to the interface, wherein a memory module is coupled to each of the plurality of memory controllers; and

a block data striper coupled to the interface and to the plurality of memory controllers.

22. The apparatus in claim 21, wherein the block striper is operable for block striping data to write data to or to read data from a plurality of channels coupled with a plurality of storage devices or memory modules, and the block striper further comprises:

an input receiving (i) an input logical block address (LBA) for a block of data, (ii) an input sector count for the block of data, and (iii) a read or write command for the block of data;

a first divider unit configured for dividing the received input LBA by a number of channels of the plurality of channels to compute a first quotient result that includes;

(i) an output divided LBA that is passed to each channel, and (ii) an output divided remainder (modulus); and

a first logic unit using the output divided remainder (modulus) to determine a selected starting channel for a block striped read or write operation.

23. The apparatus of claim 22, further comprising:

a second divider unit dividing the input sector count by the number of channels to compute a second quotient result that includes (iii) an output divided sector count for each of the plurality of channels, and (iv) an output divided sector count remainder (modulus); and

a second logic unit using the divided sector count remainder (modulus) to determine an exact sector count for each channel of the plural channel data block striped read or write operation.

24. The apparatus of claim 23, further comprising:

an execution unit executing the received read or write command by reading data from or to writing data to the plurality of channels as blocks using the determined selected starting channel and sector count for each channel and each memory device.

25. The apparatus of claim 21, wherein the block striper comprises:

a computation logic unit that receives a logical block address (LBA) and divides the received LBA by a number of channels of a storage system having a plurality of channels to computer a quotient result that becomes a new divided result LBA that is passed to each channel and a division remainder to identify a starting channel among the plurality of channels for the read or write operation.

26. The apparatus of claim 21, wherein the memory modules comprise solid state memory modules.

27. The apparatus of claim 26, wherein the solid state memory modules comprise FLASH memory modules coupled with the memory controllers, and the memory controllers comprise FLASH memory controllers coupled with the interface.

28. The apparatus of claim 27, wherein:

the FLASH memory controllers comprise a first FLASH memory controller coupled to the interface, and a second FLASH memory controller coupled to the interface;

the first FLASH memory module is coupled to the first FLASH memory controller; and

the second FLASH memory module is coupled to the second FLASH memory controller.

29. The apparatus in claim 21, further comprising at least a first bridge configured to perform a data protocol translation from a first data protocol to a second data protocol, and optionally a first data address translation to a second data address translation.

30. The apparatus in claim 29, further comprising a second bridge configured to perform a data protocol translation from the second data protocol to a third data protocol, and optionally a second data address translation to a third data address translation.

31. The apparatus in claim 21, further comprising:

a first bridge;

a second bridge coupled to the first bridge; and

the interface is coupled to the second bridge.

32. The apparatus in claim 31, wherein:

the first bridge comprises an SATA to ATA bridge;

the second bridge comprises an ATA to USB bridge; and

the interface comprises a USB interface.

33. A method, comprising:

receiving data having a first data format via a first bus;

translating the data received data from the first format into a second data format;

separating the translated data into blocks;

packaging the translated data in blocks for transmission;

transferring the data in blocks in a third data format; and

storing the transferred data in blocks in a set of FLASH memory modules.

34. The method of claim 33, further comprising:

receiving a logical block address (LBA); and

dividing the received LBA by a number of channels of a storage system having a plurality of channels to computer a quotient result that becomes a new divided result LBA that is passed to each channel and a division remainder to identify a starting channel among the plurality of channels for the read or write operation.

35. The method in claim 33, wherein:

the first data format comprises an SATA data format;

the second data format comprises an ATA data format; and

the third data form a comprises a USB data format.

36. A method comprising:

receiving a data request in a first data format;

translating the request into a third data format;

relaying the request to memory based on block locations of the request;

retrieving corresponding data from memory;

transferring the corresponding data in the third data format;

transforming the corresponding data to the first data format; and

transferring the corresponding data as a response to the request.

37. The method in claim 36, wherein:

the first data format comprises an SATA data format; and

the third data form a comprises a USB data format.

38. The method of claim 36, further comprising:

receiving a logical block address (LBA); and

dividing the received LBA by a number of channels of a storage system having a plurality of channels to computer a quotient result that becomes a new divided result LBA that is passed to each channel and a division remainder to identify a starting channel among the plurality of channels for the read or write operation.