SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY

• US 20100229035A1
• Filed: 10/31/2007
• Published: 09/09/2010
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: McPartland, Richard J., Werner, Wayne E., Kohler, Ross A.
• Granted Patent: US 8,139,412 B2
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.

Claims

1. A method of error correction for systemic errors in data read from a multi-level cell (MLC) memory, the method comprising the steps of:

reading calibration data from the MLC memory;

comparing the read calibration data to correct calibration data;

detecting systematic errors in the read calibration data based on the comparison;

determining drift for the systematic errors;

generating one or more feedback signals based on the determined drift; and

correcting for the drift based on the one or more feedback signals.

2. The invention of claim 1, wherein the step of detecting drift for the systematic errors detects at least one of sense amplifier output drift and output signal drift.

3. The invention of claim 2, wherein the step of generating one or more feedback signals generates a multiplexer feedback signal, and the step of correcting for the drift comprises the steps of applying the multiplexer feedback signal to a multiplexer and correcting for output signal drift of the multiplexer.

4. The invention of claim 2, wherein the step of generating one or more feedback signals generates a sense amplifier feedback signal, and the step of correcting for the drift comprises the steps of applying the sense amplifier feedback signal to at least one of a plurality of sense amplifiers and correcting for sense amplifier output drift of the sense amplifier.

5. The invention of claim 2, wherein the step of generating one or more feedback signals generates an MLC driver feedback signal, and the step of correcting for the drift comprises the steps of applying the MLC driver feedback signal to a row driver of an MLC.

6. The invention of claim 1, wherein the method further comprises the step of reading a sector of stored data within the MLC memory.

7. The invention of claim 6, wherein the method further comprises the step of applying error correction to a substring of bits of the sector of stored data.

19. The invention of claim 1, wherein the calibration data comprise bits stored in the MLC memory.

8. Apparatus for error correction for systemic errors in data read from a multi-level cell (MLC) memory, the apparatus comprising:

an error processor adapted to;

i) read calibration data from the MLC memory,

ii) compare the read calibration data to correct calibration data,

iii) detect systematic errors in the read calibration data based on the comparison, and

iv) determine drift for systematic errors; and

error correction control circuitry (ECCC) coupled to the error processor, wherein the ECCC is adapted to generate one or more feedback signals based on the determined drift for correction of the drift based on the one or more feedback signals.

9. The invention of claim 8, wherein:

the multi-level cell (MLC) memory includes a memory array having a plurality of MLCs, a multiplexer, and a plurality of sense amplifiers coupled between the memory array and the multiplexer;

the error processor is coupled to the multiplexer to read the calibration data,

the ECCC is coupled to at least one of the memory array, the plurality of sense amplifiers, and the multiplexer.

10. The invention of claim 9, wherein the error processor is adapted to detect at least one of sense amplifier output drift and output signal drift.

11. The invention of claim 10, wherein the one or more feedback signals comprises a multiplexer feedback signal, and the ECCC is adapted to apply the multiplexer feedback signal to the multiplexer to correct for output signal drift of the multiplexer.

12. The invention of claim 10, wherein the one or more feedback signals comprises a sense amplifier feedback signal, and the ECCC is adapted to apply the sense amplifier feedback signal to at least one of the plurality of sense amplifiers to correct for sense amplifier output drift of the sense amplifier.

13. The invention of claim 10, wherein the one or more feedback signals comprises an MLC driver feedback signal, and the ECCCC is adapted to apply the MLC driver feedback signal to a row driver of the MLC memory.

14. The invention of claim 9, wherein one or more of the plurality of MLCs are implemented as a MOSFET (metal-oxide-semiconductor field-effect transistor) transistor with either an ONO gate storage structure or a poly-silicon gate storage structure.

15. The invention of claim 9, wherein the multiplexer is an analog multiplexer and each of the plurality of sense amplifiers generates an analog output value representing a charge level corresponding to a bit value of a corresponding one of the plurality of MLCs.

16. The invention of claim 9, wherein the multiplexer is a digital multiplexer and each of the plurality of sense amplifiers generates a digital output value representing a charge level corresponding to an N-bit value of a corresponding one of the plurality of MLCs, N being an integer greater than 1.

17. The invention of claim 8, wherein the apparatus is embodied in an integrated circuit.

18. The invention of claim 17, wherein the apparatus is integrated with the MLC memory.

20. The invention of claim 8, wherein the calibration data comprise bits stored in the MLC memory.