Cable Interconnection Techniques
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Abstract
Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.
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Citations
32 Claims
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1-14. -14. (canceled)
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15. A system comprising:
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a transmitter to form multiple signals from a source signal; a receiver; at least four sets of differential conductors communicatively coupled to the transmitter, each of the sets to transmit one of the multiple signals from the transmitter to the receiver, wherein each of the at least four sets of conductors are capable of signal transmission in accordance with 10GBASE-KR in IEEE 802.3ap (2007) and an aggregate transmission rate of the signals transmitted over the four sets is approximately four times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007). - View Dependent Claims (16, 17, 18)
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19. An apparatus comprising:
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a forward error correction (FEC) layer logic, the FEC layer logic comprising FEC encoder logic and FEC decoder logic and a physical coding sublayer (PCS) sublayer logic, wherein the PCS sublayer logic provides at least two lanes to the FEC encoder logic; the PCS sublayer logic receives at least two lanes from the FEC decoder logic; the FEC encoder logic is to encode content using (2112,
2080) code blocks on each of the lanes, wherein encoding takes place independently on each of the lanes,the FEC decoder logic is to decode (2112,
2080) code blocks independently on each of the lanes and is to provide 64B/66B blocks,the FEC decoder logic is to indicate error through sync bits to the PCS sublayer logic, signals transmitted over the lanes are derived from a same signal source, and an aggregate transmission rate of the signals transmitted over the lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007). - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. An apparatus comprising:
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forward error correction (FEC) layer logic, the FEC layer logic comprising FEC encoder logic and FEC decoder logic; a PMA sublayer logic; and a PCS sublayer logic communicatively coupled to the PMA sublayer logic, wherein the PMA sublayer logic provides at least two lanes to the FEC encoder logic; the PMA sublayer logic receives at least two lanes from the FEC decoder logic; the FEC encoder logic is to encode content using (2112,
2080) code blocks on each of the lanes, wherein encoding takes place independently on each of the lanes,the FEC decoder logic is to decode (2112,
2080) code blocks independently on each of the lanes and is to provide 64B/66B blocks,the FEC decoder logic is to indicate error through sync bits to the PCS sublayer logic signals transmitted over the lanes are derived from a same signal source, and an aggregate transmission rate of the signals transmitted over the lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007). - View Dependent Claims (31, 32)
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Specification