Circuit design supporting apparatus and circuit design supporting method

• US 20100229138A1
• Filed: 03/04/2010
• Published: 09/09/2010
• Est. Priority Date: 03/05/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Nonaka, Junpei
• Granted Patent: US 8,413,092 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element substitution performing section configured to substitute an element arranged in the observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct the failure analysis based on a data of the observation portion. The element substitution performing section includes a timing analyzing section configured to perform timing analysis of the integrated circuit shown by a netlist; a delay calculating section configured to calculate a delay in the integrated circuit based on a result of the timing analysis by said timing analyzing section and said netlist; a substitution element determining section configured to specify a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element; and an element substituting section configured to update said netlist to form a new netlist.

Claims

1. A circuit design supporting apparatus comprising:

an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and

an element substitution performing section configured to substitute an element arranged in said observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct said failure analysis based on a data of said observation portion.

2. The circuit design supporting apparatus according to claim 1, wherein said element substitution performing section comprises:

a timing analyzing section configured to perform timing analysis of the integrated circuit shown by a netlist;

a delay calculating section configured to calculate a delay in the integrated circuit based on a result of the timing analysis by said timing analyzing section and said netlist;

a substitution element determining section configured to specify a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element; and

an element substituting section configured to update said netlist to form a new netlist,

wherein said delay calculating section calculates a delay change when substituting said element arranged in said observation portion by said analysis target element,

wherein said substitution element determining section configured to generate an instruction to said element substituting section to substitute said substitution candidate element by said analysis target element, if said delay change when said substitution candidate element is substituted by said analysis target element is within a preset timing margin, and

wherein said element substituting section substitutes said substitution candidate element by said analysis target element so as to form said new netlist, in response to said instruction from said substitution element determining section.

3. The circuit design supporting apparatus according to claim 2, wherein said substitution element determining section inhibits the substitution of said substitution candidate element to said analysis target element, when said delay change exceeds the preset timing margin.

4. The circuit design supporting apparatus according to claim 3, wherein said substitution element determining section outputs the instruction to said element substituting section so as to substitute said substitution candidate element by said analysis target element, when a plurality of said substitution candidate elements are contained in said observation portion, and said delay change when at least one of said plurality of substitution candidate elements is substituted to said analysis target element is within the preset timing margin.

5. The circuit design supporting apparatus according to claim 2, further comprising:

an element, arranging section configured to generate an element layout data based on said netlist,

wherein said timing analyzing section executes the timing analysis of the integrated circuit which is configured based on said netlist and said element layout data.

6. The circuit design supporting apparatus according to claim 2, further comprising:

an interconnecting section configured to execute interconnection,

wherein said interconnecting section determines an interconnection layout of the integrated circuit which is configured based on said netlist and said element layout data, and

wherein said observation portion specifying section refers to said interconnection layout determined by said interconnecting section, to specify the first portion with the high analysis easy effect as said observation portion based on said netlist, said element layout data and said interconnection layout.

7. The circuit design supporting apparatus according to claim 2, wherein said element substitution performing section further comprises a substitution candidate element extracting section,

wherein said substitution candidate element extracting section extracts as a specific substitution candidate element, the element which is present on a path in a setup timing violation, which can be canceled or be reduced by increasing a size of said element, based on a timing violation path data which indicates the path in the setup timing violation outputted from said timing analyzing section and the delay change after the element substitution outputted from said delay calculating section, and supplies the specific substitution candidate element data which contains a list of the extracted specific substitution candidate element to said element substitution determining section, and

wherein said substitution element determining section generates an instruction to said element substituting section so as to substitute said specific substitution candidate element by said analysis target element, if said delay change when said specific substitution candidate element is substituted by said analysis target element is within a preset timing margin.

8. The circuit design supporting apparatus according to claim 2, further comprising an element moving section,

wherein said element moving section moves said analysis target element into a free space when an element adjacent to said substitution candidate element and said analysis target element overlap.

10. The circuit design supporting apparatus according to claim 1, wherein said observation portion specifying section extracts equivalent failure groups G1 to GI (I is an integer equal to or more than 1) of failures which failure points cannot be specified in the integrated circuit by external measurement, from said netlist,

wherein a parameter Di (i=1 to I) to said equivalent failure group Gi is defined by the following equation:

Di=Ji·

Pi

 

where the number of nets which are contained in said equivalent failure group Gi is Ji, and a probability that failure is contained in said equivalent failure group Gi is Pi,

wherein a summation of said parameters Di is defined as an analysis difficulty degree M, and a decrease rate of said analysis difficult degree M through insertion of the observation portion is defined as the analysis easiness improvement effect, and

a point where said observation portion is inserted based on the analysis easiness improvement effect is said observation portion position.

11. The circuit design supporting apparatus according to claim 10, wherein said observation portion specifying section calculates said probability Pi that the failure is contained in said equivalent failure group Gi, based on at least one of:

a length of an interconnection which are contained in said equivalent failure group Gi, a distance between an adjacent interconnection adjacent to said interconnection and said interconnection, a length for which said interconnection and said adjacent interconnection are in parallel, and the number of vias which are contained in said equivalent failure group Gi.

9. The circuit design supporting apparatus according to claim B, wherein said element moving section returns said analysis target element to a position of said substitution candidate element before the substitution, when a distance between said analysis target element and said free space exceeds a predetermined value.

12. A circuit design supporting method comprising;

specifying, by an observation portion specifying section, a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and

substituting, by an element substitution performing section, an element arranged in said observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct said failure analysis based on a data of said observation portion,

wherein said substituting an element arranged in said observation portion comprises;

performing timing analysis of the integrated circuit shown by a netlist;

calculating a delay in the integrated circuit based on a result of the timing analysis and said netlist;

specifying a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element; and

updating said netlist to form a new netlist,

wherein said calculating a delay comprises;

calculating a delay change when substituting said element arranged in said observation portion by said analysis target element,

wherein said specifying a fine element comprises;

generating an instruction to said element substituting section to substitute said substitution candidate element by said analysis target element, if said delay change when said substitution candidate element is substituted by said analysis target element is within a preset timing margin, and

wherein said updating comprises;

forming said new netlist by substituting said substitution candidate element by said analysis target element in response to said instruction from said substitution element determining section.

13. The circuit design supporting method according to claim 12, wherein said specifying a fine element comprises:

inhibiting the substitution of said substitution candidate element to said analysis target element, when said delay change exceeds the preset timing margin.

14. The circuit design supporting method according to claim 13, wherein said specifying a fine element comprises:

generating the instruction to said element substituting section so as to substitute said substitution candidate element by said analysis target element, if a plurality of said substitution candidate elements are contained in said observation portion, and if said delay change when at least one of said plurality of substitution candidate elements is substituted to said analysis target element is within the preset timing margin.

15. The circuit design supporting method according to claim 12, further comprising:

generating an element layout data based on said netlist,

wherein said performing timing analysis comprises;

executing the timing analysis of the integrated circuit which is configured based on said netlist and said element layout data.

16. The circuit design supporting method according to claim 12, further comprising:

determining an interconnection layout of the integrated circuit which is configured based on said netlist and said element layout data,

wherein said specifying a first portion with a high improvement effect of analysis easiness comprises;

referring to said determined interconnection layout, to specify the first portion with the high analysis easy effect as said observation portion based on said netlist, said element layout data and said interconnection layout.

17. The circuit design supporting method according to claim 12, wherein said substituting an element arranged in said observation portion comprises:

extracting a substitution candidate element,

wherein said extracting a substitution candidate element comprises;

extracting as a specific substitution candidate element, the element which is present on a path in a setup timing violation that can be canceled or be reduced by increasing a size of said element, based on a timing violation path data which indicates the path in the setup timing violation and the delay change after the element substitution; and

supplying the specific substitution candidate element data which contains a list of the extracted specific substitution candidate element to said element substitution determining section, and

wherein said specifying a fine element comprises;

generating an instruction to said element substituting section so as to substitute said specific substitution candidate element by said analysis target element, if said delay change when said specific substitution candidate element is substituted by said analysis target element is within a preset timing margin.

18. The circuit design supporting method according to claim 12, further comprising:

moving said analysis target element into a free space when an element adjacent to said substitution candidate element and said analysis target element overlap.

19. The circuit design supporting method according to claim 18, wherein said moving said analysis target element comprises:

returning said analysis target element to a position of said substitution candidate element before the substitution, when a distance between said analysis target element and said free space exceeds a predetermined value.

20. A computer-readable recording medium in which a computer-executable program code is stored to realize a circuit design supporting method which comprises:

specifying, by an observation portion specifying section, a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and

substituting, by an element substitution performing section, an element arranged in said observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct said failure analysis based on a data of said observation portion,

wherein said substituting an element arranged in said observation portion comprises;

performing timing analysis of the integrated circuit shown by a netlist;

calculating a delay in the integrated circuit based on a result of the timing analysis and said netlist;

specifying a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element; and

updating said netlist to form a new netlist,

wherein said calculating a delay comprises;

calculating a delay change when substituting said element arranged in said observation portion by said analysis target element,

wherein said specifying a fine element comprises;

generating an instruction to said element substituting section to substitute said substitution candidate element by said analysis target element, if said delay change when said substitution candidate element is substituted by said analysis target element is within a preset timing margin, and

wherein said updating comprises;

forming said new netlist by substituting said substitution candidate element by said analysis target element in response to said instruction from said substitution element determining section.

21. The computer-readable recording medium according to claim 20, wherein said specifying a fine element comprises:

inhibiting the substitution of said substitution candidate element to said analysis target element, when said delay change exceeds the preset timing margin.

22. The computer-readable recording medium according to claim 21, wherein said specifying a fine element comprises:

generating the instruction to said element substituting section so as to substitute said substitution candidate element by said analysis target element, if a plurality of said substitution candidate elements are contained in said observation portion, and if said delay change when at least one of said plurality of substitution candidate elements is substituted to said analysis target element is within the preset timing margin.

23. The computer-readable recording medium according to claim 20, wherein said circuit design supporting method further comprises:

generating an element layout data based on said netlist,

wherein said performing timing analysis comprises;

executing the timing analysis of the integrated circuit which is configured based on said netlist and said element layout data.

24. The computer-readable recording medium according to claim 20, wherein the circuit design supporting method further comprises:

determining an interconnection layout of the integrated circuit which is configured based on said netlist and said element layout data, and

wherein said specifying a first portion with a high improvement effect of analysis easiness comprises;

referring to said determined interconnection layout, to specify the first portion with the high analysis easy effect as said observation portion based on said netlist, said element layout data and said interconnection layout.

25. The computer-readable recording medium according to claim 20, wherein said substituting an element arranged in said observation portion comprises:

extracting a substitution candidate element,

wherein said extracting a substitution candidate element comprises;

extracting as a specific substitution candidate element, the element which is present on a path in a setup timing violation that can be canceled or be reduced by increasing a size of said element, based on a timing violation path data which indicates the path in the setup timing violation and the delay change after the element substitution; and

supplying the specific substitution candidate element data which contains a list of the extracted specific substitution candidate element to said element substitution determining section,

wherein said specifying a fine element comprises;

generating an instruction to said element substituting section so as to substitute said specific substitution candidate element by said analysis target element, if said delay change when said specific substitution candidate element is substituted by said analysis target element is within a preset timing margin.

26. The computer-readable recording medium according to claim 20, wherein said circuit design supporting method further comprises:

moving said analysis target element into a free space when an element adjacent to said substitution candidate element and said analysis target element overlap.

27. The computer-readable recording medium according to claim 26, wherein said moving said analysis target element comprises:

returning said analysis target element to a position of said substitution candidate element before the substitution, when a distance between said analysis target element and said free space exceeds a predetermined value.