PIXEL SENSOR CELL INCLUDING LIGHT SHIELD

• US 20100230729A1
• Filed: 08/10/2009
• Published: 09/16/2010
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ellis-Monaghan, John, Gambino, Jeffrey P., Rassel, Richard J., Jaffe, Mark D.
• Granted Patent: US 9,543,356 B2
• Time in Patent Office: Days
• US Class Current: 257/228
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate

Claims

1. A pixel sensor cell comprising:

a second transistor located within a second semiconductor layer located over a carrier substrate;

a photoactive region located within a first semiconductor layer located over the second semiconductor layer and the carrier substrate; and

a light blocking layer located interposed between the first semiconductor layer and the second semiconductor layer and shielding the second transistor from back side illumination.

2. The pixel sensor cell of claim 1 further comprising a first transistor located within the first semiconductor layer and not shielded by the light blocking layer.

3. The pixel sensor cell of claim 2 wherein the light blocking layer comprises a gate for the first transistor.

4. The pixel sensor cell of claim 1 further comprising a floating diffusion region that is also located within the second semiconductor layer and shielded by the light blocking layer.

5. A pixel sensor cell comprising

a dielectric isolated metallization stack located over a carrier substrate and including a thin film transistor and a metal-insulator-metal capacitor that are shielded by a light blocking layer;

a semiconductor layer located over the dielectric isolated metallization stack and the carrier substrate and including a photoactive region.

6. The pixel sensor cell of claim 5 wherein the light blocking layer comprises a metallization layer within the dielectric isolated metallization stack.

7. The pixel sensor cell of claim 5 wherein the semiconductor layer includes at least one transistor in addition to the photoactive region.

8. The pixel sensor cell of claim 5 wherein the pixel sensor cell is designed to transfer charge from the floating diffusion region through the thin film transistor and onto a metal insulator metal capacitor.

9. A method for fabricating a pixel sensor cell comprising:

forming over a sacrificial substrate a first semiconductor layer that includes a photoactive region;

forming over the first semiconductor layer a light blocking layer;

forming over the light blocking layer a second semiconductor layer that includes at least in part a second transistor that is shielded by the light blocking layer;

affixing a carrier substrate over the second semiconductor layer; and

removing the sacrificial substrate.

10. The method of claim 9 wherein the forming the first semiconductor layer includes a first transistor at least in-part within the first semiconductor layer.

11. The method of claim 10 wherein the first transistor is not shielded by the light blocking layer.

12. The method of claim 10 wherein the light blocking layer serves as gate for the first transistor.

13. The method of claim 9 wherein the forming the second semiconductor layer includes a floating diffusion region within the second semiconductor layer.

14. The method of claim 13 wherein the floating diffusion region is shielded by the light blocking layer.

15. A method for fabricating a pixel sensor cell comprising:

forming over a sacrificial substrate a first semiconductor layer that includes a photoactive region;

forming over the first semiconductor layer a dielectric isolated metallization stack including a thin film transistor and a metal-insulator-metal capacitor that are shielded by a light blocking layer;

affixing a carrier substrate over the dielectric isolated metallization stack; and

removing the sacrificial substrate.

16. The method of claim 15 wherein the light blocking layer comprises a metallization layer within the dielectric isolated metallization stack.

17. The method of claim 15 wherein the first semiconductor layer includes at least one transistor in addition to the photoactive region.

18. The method of claim 15 wherein the pixel sensor cell is designed to transfer charge from the floating diffusion region through the thin film transistor and onto the metal-insulator-metal capacitor.

19. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a pixel sensor cell comprising a second transistor located within a second semiconductor layer located over a carrier substrate;

a photoactive region located within a first semiconductor layer located over the second semiconductor layer and the carrier substrate; and

a light blocking layer located interposed between the first semiconductor layer and the second semiconductor layer and shielding the second transistor from back side illumination.