VERTICAL GATED ACCESS TRANSISTOR
First Claim
1. A method of forming an integrated circuit, the method comprising:
- forming a plurality of U-shaped semiconductor structures in a first region of a substrate;
depositing a layer of conductive material over the first region and a second region of the substrate;
etching a pattern into the layer of conductive material over the first region of the substrate, wherein etching the pattern further comprises forming a plurality of active device elements from the layer of conductive material over the second region of the substrate;
protectively masking the second region of the substrate to protect the layer of conductive material in the second region; and
etching a plurality of trenches in the first region using the pattern of the layer of conductive material in the first region as an etch mask while the second region of the substrate is protectively masked.
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Accused Products
Abstract
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.
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Citations
26 Claims
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1. A method of forming an integrated circuit, the method comprising:
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forming a plurality of U-shaped semiconductor structures in a first region of a substrate; depositing a layer of conductive material over the first region and a second region of the substrate; etching a pattern into the layer of conductive material over the first region of the substrate, wherein etching the pattern further comprises forming a plurality of active device elements from the layer of conductive material over the second region of the substrate; protectively masking the second region of the substrate to protect the layer of conductive material in the second region; and etching a plurality of trenches in the first region using the pattern of the layer of conductive material in the first region as an etch mask while the second region of the substrate is protectively masked. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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a semiconductor substrate having an array portion and a logic portion; at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate; a gate electrode formed adjacent sidewalls of the U-shaped semiconductor structure and between the first and second pillars; and at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A memory device comprising:
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a substrate having an array portion and a logic portion; a plurality of U-shaped semiconductor structures that are formed in the array portion of the substrate, wherein the U-shaped semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches having depths between those of the shallow and deep trenches; and a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification