INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD

• US 20100230764A1
• Filed: 03/12/2009
• Published: 09/16/2010
• Est. Priority Date: 03/12/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meyer, Thorsten, Decker, Stefan, Krischke, Norbert, Kadow, Christoph
• Granted Patent: US 8,643,068 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Claims

1. An integrated circuit, comprising:

a first FET and a second FET,

wherein at least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET,

at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively; and

a dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

2. The integrated circuit of claim 1, comprising wherein the dopant concentration of the body of each of the first and second FETs is declining along the channel from the peak location to a pn junction between body and source.

3. The integrated circuit of claim 1, comprising wherein the dopant concentration of the body of each of the first and second FETs is constant along the channel between a pn junction between body and source and the peak location within the channel, the dopant concentration declining from the peak location to the drain.

4. The integrated circuit of claim 1, comprising wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

5. The integrated circuit of claim 1, comprising wherein the dopant concentration of the body of each of the first and second FETs has multiple peaks along the channel.

6. The integrated circuit of claim 5, comprising wherein the multiple peaks have a same maximum dopant concentration.

7. The integrated circuit of claim 1, comprising wherein the dopant concentration of the body of each of the first and second FETs has a single peak within the channel, the dopant concentration declining to both ends of the channel in the direction of source and drain.

8. The integrated circuit of claim 1, comprising wherein the first FET is a power FET and the second FET is a sense FET having an area that is smaller than the area of the power FET.

9. The integrated circuit of claim 1, comprising:

wherein the gate of the first FET is connected to the gate of the second FET;

one of source and drain of the first FET is connected to the corresponding one of source and drain of the second FET; and

wherein the other one of source and drain of the first FET and the other one of source and drain of the second FET are connected to the circuit element.

10. An integrated circuit, comprising:

a first FET and a second FET,

wherein at least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET, and wherein at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively; and

wherein a dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel, the dopant concentration declining along the channel from the peak location to a pn junction between body and source.

11. The integrated circuit of claim 10, comprising wherein the dopant concentration of the body of each of the first and second FETs has multiple peaks along the channel.

12. The integrated circuit of claim 10, comprising wherein the dopant concentration of the body of each of the first and second FETs has a single peak within the channel, the profile declining to both ends of the channel in the direction of source and drain.

13. The integrated circuit of claim 10, comprising wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

14. The integrated circuit of claim 10, comprising wherein the first FET is a power FET and the second FET is a sense FET having an area that is smaller than the area of the power FET.

15. The integrated circuit of claim 10, comprising wherein the gate of the first FET is connected to the gate of the second FET;

one of source and drain of the first FET is connected to the corresponding one of source and drain of the second FET; and

wherein the other one of source and drain of the first FET and the other one of source and drain of the second FET are connected to the circuit element.

16. A method of forming an integrated circuit, comprising:

forming a first FET and a second FET;

electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate of the second FET; and

connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET to a circuit element, respectively; and

wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant concentration along a channel of the respective FET that includes a peak at a peak location within the channel.

17. The method of claim 16, comprising forming the first and second FETs as Trench FETs, and forming the body of each of the first and second FETs includes:

implanting dopants into a semiconductor substrate such that a peak concentration of the implanted dopants is deeper within the semiconductor substrate than a pn junction between source and body.

18. The method of claim 17, comprising implanting the dopants into the semiconductor substrate at different implant energies such that multiple peak concentrations of the implanted dopants are deeper within the substrate than the pn junction between source and body.

19. The method of claim 16, comprising forming the first and second FETs as lateral FETs, and forming the body of each of the first and second FETs includes implanting dopants into an area of a semiconductor substrate;

the method further comprising;

forming a gate dielectric and a gate electrode at least partly on the area of the semiconductor substrate.

20. The method of claim 16, comprising forming the body of each of the first and second FETs includes:

implanting dopants into a semiconductor substrate and annealing implant damages such that a fraction of a channel area of each of the first and second FETs having a dopant concentration of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

21. The method of claim 16, further comprising:

forming the first FET as a power FET and forming the second FET as a sense FET having an area that is smaller than the area of the power FET.

22. The method of claim 16, further comprising:

connecting the gate of the first FET to the gate of the second FET;

connecting one of source and drain of the first FET to the corresponding one of source and drain of the second FET; and

connecting the other one of source and drain of the first FET and the other one of source and drain of the second FET to the circuit element.

23. An integrated circuit comprising:

a first FET coupled to a second FET;

a doping concentration of a body along a channel of the first FET and the second FET configured to provide matching threshold voltages of the first FET and the second FET.

24. The integrated circuit of claim 23, comprising:

the dopant concentration having a maximum dopant concentration at a peak location within the channel.