TERMINATION FOR A SUPERJUNCTION DEVICE

• US 20100230775A1
• Filed: 02/09/2010
• Published: 09/16/2010
• Est. Priority Date: 01/26/2006
• Status: Active Grant

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Sridevan, Srinkant, Husain, Ali
• Granted Patent: US 8,633,561 B2
• Time in Patent Office: Days
• US Class Current: 257/487
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Abstract

A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.

Claims

1. (canceled)

2. A power semiconductor device comprising:

a semiconductor body of first conductivity;

an active region formed in said semiconductor body; and

a termination region adjacent said active region, wherein said termination region comprises a first plurality of columns of a second conductivity positioned to form corners and a center of a hexagon, wherein each two adjacent columns and a column at said center of said hexagon form vertices of a first plurality of equilateral triangles, and wherein said first plurality of columns have substantially analogous resistivity.

3. The power semiconductor device of claim 2, wherein said termination region further comprises a second plurality of columns of a third conductivity, wherein each column of said second plurality of columns is positioned equidistance from two adjacent columns of said first plurality of columns.

4. The power semiconductor device of claim 3, wherein each column in said second plurality of columns is disposed on a side of a respective equilateral triangle of said first plurality of equilateral triangles.

5. The power semiconductor device of claim 4, wherein said termination region further comprises a third plurality of columns of a fourth conductivity, wherein each column of said third plurality of columns is disposed at a center of a respective equilateral triangle of said first plurality of equilateral triangles.

6. The power semiconductor device of claim 5, wherein columns of said second plurality of columns and columns of said first plurality of columns form vertices of a second plurality of equilateral triangles, wherein said termination region further comprises a fourth plurality of columns of a fifth conductivity, and wherein each column of said fourth plurality of columns is positioned at a center of a respective equilateral triangle of said second plurality of equilateral triangles.

7. The power semiconductor device of claim 4, wherein said termination region further comprises a fifth plurality of columns, wherein said second plurality of columns and said first plurality of columns form vertices of a second plurality of equilateral triangles, and wherein columns of said fifth plurality of columns are disposed on a side of a respective equilateral triangle of said third plurality of triangles, and wherein columns of said fifth plurality of columns are equidistance from two adjacent vertices of a respective equilateral triangle of said second plurality of equilateral triangles.

8. The power semiconductor device of claim 3, wherein each column of said second plurality of columns is positioned at a center of a respective equilateral triangle of said first plurality of equilateral triangles, wherein each two adjacent columns of said second plurality of columns and a column at said center of said hexagon form vertices of a third plurality of equilateral triangles.

9. The power semiconductor device of claim 8 further comprising a sixth plurality of columns of a seventh conductivity, wherein each column of said sixth plurality of columns is positioned at a center of a respective equilateral triangle of said third plurality of equilateral triangles.

10. The power semiconductor device of claim 2, further comprising a race track termination disposed around said termination region between said termination region and the edges of said semiconductor device.

11. The power semiconductor device of claim 2, wherein a breakdown voltage is increased by increasing a density of said first plurality of columns and decreasing a width of said first plurality of columns.

12. A method for improving the breakdown at the termination of a superjunction power semiconductor device, said method comprising:

forming an active region in said superjunction power semiconductor device; and

forming a termination region adjacent to said active region of said superjunction power semiconductor device of first conductivity, wherein said termination region comprises a first plurality of columns of a second conductivity positioned to form corners and a center of a hexagon, wherein each two adjacent columns and a column at said center of said hexagon forms vertices of a first plurality of equilateral triangles, and wherein said first plurality of columns have substantially analogous resistivity.

13. The method of claim 12, wherein said termination region further comprises a second plurality of columns of a third conductivity, wherein each column of said second plurality of columns is positioned equidistance from two adjacent columns of said first plurality of columns.

14. The method of claim 13, wherein each column in said second plurality of columns is disposed on a side of a respective equilateral triangle of said first plurality of equilateral triangles.

15. The method of claim 14, wherein said termination region further comprises a third plurality of columns of a fourth conductivity, wherein each column of said third plurality of columns is disposed at a center of a respective equilateral triangle of said first plurality of equilateral triangles.

16. The method of claim 15, wherein columns of said second plurality of columns and columns of said first plurality of columns form vertices of a second plurality of equilateral triangles, wherein said termination region further comprises a fourth plurality of columns of a fifth conductivity, and wherein each column of said fourth plurality of columns is positioned at a center of a respective equilateral triangle of said second plurality of equilateral triangles.

17. The method of claim 14, wherein said termination region further comprises a fifth plurality of columns, wherein said second plurality of columns and said first plurality of columns form vertices of a second plurality of equilateral triangles, and wherein columns of said fifth plurality of columns are disposed on a side of a respective equilateral triangle of said third plurality of triangles, and wherein columns of said fifth plurality of columns are equidistance from two adjacent vertices of a respective equilateral triangle of said second plurality of equilateral triangles

18. The method of claim 13, wherein each column of said second plurality of columns is positioned at a center of a respective equilateral triangle of said first plurality of equilateral triangles, wherein each two adjacent columns of said second plurality of columns and a column at said center of said hexagon form vertices of a third plurality of equilateral triangles.

19. The method of claim 18 further comprising:

forming a sixth plurality of columns of a seventh conductivity, wherein each column of said sixth plurality of columns is positioned at a center of a respective equilateral triangle of said third plurality of equilateral triangles.

20. The method of claim 12 further comprising:

forming a race track termination region disposed around said termination region between said termination region and the edges of said semiconductor device.

21. The method of claim 12 further comprising:

increasing a breakdown voltage by increasing a density of said first plurality of columns and decreasing a width of said first plurality of columns.