Microelectronic Assemblies Having Compliancy and Methods Therefor

• US 20100230812A1
• Filed: 05/21/2010
• Published: 09/16/2010
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Ovrutsky, David, Oganesian, Vage, Gao, Guilian
• Granted Patent: US 8,115,308 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Claims

1. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

compliant bumps of dielectric material overlying the first surface of said semiconductor wafer, each said compliant bump having a planar top surface;

a dielectric layer overlying the first surface of said semiconductor wafer and at least edges of said compliant bumps, wherein the planar top surfaces of said compliant bumps and said contacts are accessible through said dielectric layer;

conductive traces electrically connected with said contacts and extending therefrom to overlie the planar top surfaces of said compliant bumps; and

conductive elements overlying the planar top surfaces in contact with said conductive traces.

2. The assembly as claimed in claim 1, wherein said conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

3. The assembly as claimed in claim 1, wherein said conductive elements include terminals of said assembly for electrical connection with corresponding contact elements of a circuit panel.

4. The assembly as claimed in claim 3, wherein said terminals include at least one terminal which is disposed singly atop one of said compliant bumps.

5. The assembly as claimed in claim 3, further comprising a circuit panel, wherein said terminals are bonded to said contact elements of said circuit panel.

6. The assembly as claimed in claim 5, wherein said terminals are solder bonded to said contact elements.

7. The assembly as claimed in claim 1, wherein said semiconductor wafer comprises one or more memory chips.

8. The assembly as claimed in claim 7, wherein said wafer comprises one or more double-data-rate (DDR) chips.

9. The assembly as claimed in claim 1, wherein the conductive elements overlie the planar top surfaces.

10. The assembly as claimed in claim 9, wherein the dielectric layer overlies the planar top surfaces of at least some of the compliant bumps and the conductive elements overlie the dielectric layer above the planar top surfaces.

11. The assembly as claimed in claim 9, further comprising openings in the dielectric layer aligned with the planar top surfaces, wherein the conductive elements are disposed within the openings.

12. The assembly as claimed in claim 1, further comprising a solder mask overlying the traces.

13. The assembly as claimed in claim 1, wherein the conductive elements include solder balls.

14. The assembly as claimed in claim 1, wherein the conductive elements include conductive posts.

15. The assembly as claimed in claim 1, wherein the conductive elements include conductive pins.

16. The assembly as claimed in claim 1, wherein the dielectric layer is a polymeric layer.

17. The assembly as claimed in claim 1, wherein the dielectric layer includes a photoimageable material.

18. The assembly as claimed in claim 17, wherein the photoimageable material includes silicone.

19. The assembly as claimed in claim 1, wherein the dielectric layer is compliant.

20. The assembly as claimed in claim 1, wherein two or more of said conductive elements are disposed atop a single one of said compliant bumps.