DRIVING LIQUID CRYSTAL DISPLAYS

• US 20100231614A1
• Filed: 12/03/2009
• Published: 09/16/2010
• Est. Priority Date: 03/16/2009
• Status: Active Grant

• Current Assignee: John Gilmore
• Original Assignee: Pixel Qi Corporation
• Inventors: Bolotski, Michael, Vieri, Carlin J.
• Granted Patent: US 8,670,004 B2
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2320/0238 Improving the black level
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

In an embodiment, a pixel driving circuit comprises: one or more source drivers for enabling a first subpixel of a subpixel pair to receive first data and a second subpixel of the subpixel pair to receive second data; one or more source drivers for driving the first data to the first subpixel and the second data to the second subpixel, wherein the first data is different than the second data.

Claims

1. A method comprising:

sending, from a first source driver, a first value to a first subpixel of a subpixel pair;

sending, from a second source driver, a second value to a second subpixel of the subpixel pair, wherein the first value is different than the second value.

2. The method of claim 1, wherein the first subpixel of the subpixel pair is a transmissive subpixel and the second subpixel of the subpixel pair is a reflective subpixel.

3. The method of claim 1, wherein the first source driver is the same as the second source driver.

4. The method of claim 1, wherein the second value is a black voltage value.

5. A display panel comprising:

a pixel array with a plurality of pixels arranged in rows and columns, wherein one or more pixels of the plurality of pixels comprise one or more subpixel pairs;

first logic configured to drive a first value to a first subpixel of the subpixel pair;

second logic configured to drive a different value to a second subpixel of the subpixel pair.

6. The display panel of claim 5, further comprising:

mode selection logic configured to cause the display panel to operate in a plurality of modes comprising

a first mode wherein the different value is a black voltage value;

a second mode wherein the different value is the same as the first value.

7. The display panel of claim 5, wherein the first logic comprises two gate row drivers for each row in the pixel array and three source drivers for each row in the pixel array.

8. A pixel driving circuit comprising:

one or more gate row drivers for enabling a first subpixel of a subpixel pair to receive pixel data independently of a second subpixel of the subpixel pair receiving a different value;

a source driver for driving the pixel data to the first subpixel via a source line;

logic configured to disconnect the source driver from the source line;

value generation logic configured to drive the different value to the second subpixel of the subpixel pair.

9. The pixel driving circuit of claim 8, wherein the value generation logic is configured to drive the different value to the second subpixel via the source line.

10. The pixel driving circuit of claim 8, wherein the different value is a black voltage value.

11. A pixel driving circuit comprising:

one or more gate row drivers for enabling a first subpixel of a subpixel pair to receive data and enabling a second subpixel of the subpixel pair to receive data;

one or more source drivers configured to drive pixel data to the first subpixel and drive a preprogrammed value to the second subpixel.

12. The circuit of claim 11 further comprising:

logic for controlling the timing of driving the pixel data and the preprogrammed value.

13. The circuit of claim 11 further comprising:

logic for delivering the pixel data to the one or more source drivers.

14. The circuit of claim 11, further comprising:

mode selection logic configured to cause the display panel to operate in a plurality of modes comprising

a first mode wherein the preprogrammed value is a black voltage value;

a second mode wherein the one or more source drivers drives pixel data to the second subpixel.

15. A pixel driving circuit comprising;

first circuitry configured to store, on a first subpixel of a first subpixel pair, a first voltage value;

second circuitry configured to store, on a second subpixel of the first subpixel pair, a second voltage value.

16. The pixel driving circuit of claim 15, wherein the first subpixel is a transmissive subpixel, and the second subpixel is a reflective subpixel.

17. The pixel driving circuit of claim 15, wherein the first voltage value represents pixel data, and wherein the second voltage value is a black voltage value.

18. A pixel driving circuit comprising:

one or more gate row drivers for enabling a first subpixel of a subpixel pair to receive pixel data independently of a second subpixel of the subpixel pair receiving a different value;

one or more source drivers for driving the pixel data and the different value via one or more source lines;

logic configured to deliver the pixel data and the different value to the one or more source drivers.

19. The pixel driving circuit of claim 18, wherein the first subpixel is a transmissive subpixel and the second subpixel is a reflective subpixel

20. The pixel driving circuit of claim 18, wherein the different value is a black voltage value.

21. A pixel driving circuit comprising:

one or more gate row drivers for enabling a first subpixel of a subpixel pair to receive first data from a source line and further enabling a second subpixel of the subpixel pair to receive second data from the source line;

a source driver for driving first data to the first subpixel via the source line;

switching logic for enabling the pixel driving circuit to operate in a plurality of modes comprising

a first mode, wherein the second subpixel receives the first data from the source line and the second data is the same as the first data, or

a second mode, wherein the second subpixel receives second data that is different than the first data.

22. A pixel driving circuit comprising:

a gate row driver for enabling one or more subpixels of one or more subpixel pairs to receive data;

a source driver for driving the data to the one or more subpixels;

switching logic configured to cause the pixel driving circuit to operate in a plurality of configurations comprising

a first configuration wherein the gate row driver enables a first subpixel of a subpixel pair to receive first data from the source driver,

a second configuration wherein the gate row driver enables a second subpixel of the subpixel pair to receive second data from the source driver, the second data being different than the first data.

23. The pixel driving circuit of claim 22, wherein the switching logic is further configured to cause the pixel driving circuit to operate in a third configuration wherein the gate row driver enables the first subpixel to receive third data from the source driver and the second subpixel to receive the third data from the source driver.

24. A pixel driving circuit comprising:

one or more source drivers;

a first gate row driver configured to enable first subpixels of subpixel pairs to receive first data from the one or more source drivers;

a second gate row driver configured to enable second subpixels of the subpixel pairs to receive second data from the source driver, the second data being different than the first data.

25. The pixel driving circuit of claim 24, wherein the first subpixel pairs comprise both transmissive and reflective subpixels, and the second subpixel pairs comprise both transmissive and reflective subpixels.

26. A pixel driving circuit comprising:

a gate row driver configured to enable a first subpixel of a subpixel pair to receive first data and to enable a second subpixel of a the subpixel pair to receive second data;

a first source driver configured to drive the first data to the first subpixel;

a second source driver configured to drive the second data to the second subpixel, wherein the second data is different than the first data.

27. The pixel driving circuit of claim 26 wherein the gate row driver is further configured to enable a third subpixel of a second subpixel pair to receive third data, the pixel driving circuit further comprising:

a third source driver configured to drive the third data to the third subpixel.

28. A pixel driving circuit comprising:

a first source driver;

a first gate row driver, the first gate row driver configured to enable a first subpixel of a subpixel pair to receive first data from the first source driver;

a second source driver;

a second gate row driver, the second gate row driver configured to enable a second subpixel of the subpixel pair to receive second data, wherein the second data is different than the first data.