VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY

• US 20100232200A1
• Filed: 03/10/2010
• Published: 09/16/2010
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Granted Patent: US 8,773,881 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe

Abstract

A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F².

Claims

1. A memory device comprising:

a substrate; and

disposed over the substrate, an array of vertical memory switches each having at least three terminals and a cross-sectional area less than 6F².

2. The memory device of claim 1, wherein each memory switch has a cross-sectional area less than approximately 4F².

3. The memory device of claim 1, wherein at least one memory switch comprises a MOS transistor.

4. The memory device of claim 1, wherein at least one memory switch comprises a four-layer diode.

5. The memory device of claim 1, wherein at least two memory switches share a common gate for operating a channel of each of the memory switches.

6. The memory device of claim 1, further comprising two interleaved pluralities of bit lines for selecting a memory switch, one plurality of bit lines being connected to a first selection circuit on a first side of the array of memory switches and the other plurality of bit lines being connected to a second selection circuit on a second side of the array opposing the first side.

7. The memory device of claim 1, further comprising a first array of programmable memory elements disposed over the array of memory switches, each memory element in the first array being electrically connected to at least one of the memory switches through a conductive post.

8. The memory device of claim 7, further comprising, disposed over the first array of programmable memory elements, a second array of programmable memory elements, each memory element in the second array being electrically connected to at least one of the memory switches through a conductive post.

9. The memory device of claim 7, wherein each memory element in the first array comprises at least one of a phase-change material, a resistive-change material, or a one-time-programmable element.

10. The memory device of claim 1, further comprising peripheral circuitry electrically connected to the array of memory switches, the peripheral circuitry comprising a plurality of vertical MOS transistors.

11. The memory device of claim 1, wherein F is less than approximately 25 nm.

12. The memory device of claim 1, wherein each vertical memory switch corresponds to a single bit.

13. The memory device of claim 1, wherein each vertical memory switch corresponds to a plurality of bits.

14. A method of forming a memory device, the method comprising:

providing a substrate;

forming a source layer on the substrate;

forming a channel layer over the source layer, the channel layer having a doping type different from a doping type of the source layer;

forming a drain layer over the channel layer, the drain layer having a doping type different from a doping type of the channel layer; and

patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6F².

15. The method of claim 14, wherein patterning the source, channel, and drain layers comprises:

forming a plurality of generally parallel isolation trenches intersecting the source, channel, and drain layers;

depositing a dielectric material into the plurality of isolation trenches; and

planarizing the dielectric material such that a top surface of the dielectric material is substantially coplanar with a top surface of the drain layer.

16. The method of claim 15, wherein patterning the source, channel, and drain layers further comprises:

forming a plurality of generally parallel gate trenches intersecting the isolation trenches,

wherein each memory switch is bounded by intersecting isolation trenches and gate trenches.

17. The method of claim 16, wherein the cross-sectional area of each memory switch is less than approximately 4F².

18. The method of claim 16, further comprising:

forming a gate dielectric in contact with the channel layer within the gate trenches;

depositing a gate contact material in the gate trenches; and

planarizing the gate contact material such that a top surface of the gate contact material is substantially coplanar with a top surface of the dielectric material in the isolation trenches.

19. The method of claim 14, further comprising:

forming a conductive post over a memory switch; and

forming a programmable material in contact with the conductive post, thereby forming a programmable memory cell.

20. The method of claim 19, wherein the programmable material comprises at least one of phase-change material, a resistive-change material, or a one-time-programmable material.

21. The method of claim 19, wherein forming the programmable material comprises etching at least a portion of a dielectric material disposed around the conductive post to form a recess, at least substantially filling the recess with the programmable material, and planarizing the programmable material such that a top surface of the programmable material is substantially coplanar with a top surface of the conductive post.

22. The method of claim 21, wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only one corner of the conductive post.

23. The method of claim 21, wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only two corners of the conductive post.

24. The method of claim 14, wherein forming the source, channel, and drain layers each comprises ion implantation of dopants into the substrate.

25. The method of claim 14, wherein forming the source, channel, and drain layers each comprises deposition of a semiconductor material over the substrate.

26. The method of claim 14, further comprising, substantially simultaneously with patterning the source, channel, and drain layers into an array of memory switches, patterning the source, channel, and drain layers into a plurality of peripheral devices disposed proximate the array of memory switches.

27. The method of claim 26, further comprising electrically connecting the peripheral devices to the array of memory switches.

28. A memory device comprising:

a substrate defining a die; and

disposed over the substrate within the die, an array of vertical memory switches, each having at least three terminals and defining a memory array of at least one terabit.

29. The memory device of claim 28, wherein each vertical memory switch corresponds to a single bit.

30. The memory device of claim 28, wherein each vertical memory switch corresponds to a plurality of bits.

31. The memory device of claim 28, wherein the die has an area of 1 cm² and the memory array has at least 5 terabits.

32. The memory device of claim 28, wherein at least one memory switch comprises a MOS transistor.

33. The memory device of claim 28, wherein at least one memory switch comprises a four-layer diode.

34. The memory device of claim 28, wherein at least two memory switches share a common gate for operating a channel of each of the memory switches.

35. A memory device comprising:

a vertical conductor disposed over a substrate;

a switch for selecting the vertical conductor; and

a plurality of layers, each comprising a plurality of programmable memory elements, disposed over and electrically connected to the vertical conductor.

36. The memory device of claim 35, wherein the switch comprises a vertical memory switch having at least three terminals and a cross-sectional area less than 6F².

37. The memory device of claim 35, wherein at least one of the plurality of programmable memory elements comprises at least one of a phase-change material, a resistive-change material, or a one-time-programmable element.

38. A memory device comprising:

a first set of parallel rows of memory cells connected together;

a second set of parallel rows of memory cells connected together; and

a control conductor selectable to activate at least one of the rows of the first set and at least one of the rows of the second set,

wherein selection of (i) one of the sets, and (ii) at least one of the rows by the control conductor, causes activation of at least one row of memory cells.