VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY
First Claim
Patent Images
1. A memory device comprising:
- a substrate; and
disposed over the substrate, an array of vertical memory switches each having at least three terminals and a cross-sectional area less than 6F2.
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Abstract
A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F2.
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Citations
38 Claims
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1. A memory device comprising:
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a substrate; and disposed over the substrate, an array of vertical memory switches each having at least three terminals and a cross-sectional area less than 6F2. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of forming a memory device, the method comprising:
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providing a substrate; forming a source layer on the substrate; forming a channel layer over the source layer, the channel layer having a doping type different from a doping type of the source layer; forming a drain layer over the channel layer, the drain layer having a doping type different from a doping type of the channel layer; and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6F2. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A memory device comprising:
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a substrate defining a die; and disposed over the substrate within the die, an array of vertical memory switches, each having at least three terminals and defining a memory array of at least one terabit. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. A memory device comprising:
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a vertical conductor disposed over a substrate; a switch for selecting the vertical conductor; and a plurality of layers, each comprising a plurality of programmable memory elements, disposed over and electrically connected to the vertical conductor. - View Dependent Claims (36, 37)
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38. A memory device comprising:
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a first set of parallel rows of memory cells connected together; a second set of parallel rows of memory cells connected together; and a control conductor selectable to activate at least one of the rows of the first set and at least one of the rows of the second set, wherein selection of (i) one of the sets, and (ii) at least one of the rows by the control conductor, causes activation of at least one row of memory cells.
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Specification