ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION

• US 20100232245A1
• Filed: 03/27/2007
• Published: 09/16/2010
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Lambert, Nicolaas, Van Acht, Victor M. G.
• Granted Patent: US 7,952,949 B2
• Time in Patent Office: Days
• US Class Current: 365/210.110
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).

Claims

1. An electronic circuit comprising

a memory matrix with a plurality of columns of memory cells and bit lines coupled to the memory cells in respective ones of the columns;

a reference circuit with a reference output;

a differential sense amplifier with a first and second input,

a circuit for coupling the first input of the differential sense amplifier at least to a first one of the bit lines and the second input of the differential sense amplifier to the reference output;

a cross-coupling circuit, configured to couple at least a second one of the bit lines, which is adjacent to the first one of the bit lines, to the reference circuit, so that a bit line signal value on the second one of the bit lines will affect a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines.

2. An electronic circuit according to claim 1, wherein the cross-coupling circuit is configured to couple a plurality of second ones of the bit lines, which are adjacent on mutually opposite sides to the first one of the bit lines, to the reference circuit, so that bit line signal values on each second one of the bit lines affects the reference signal value on the reference output.

3. An electronic circuit according to claim 1, wherein the cross-coupling circuit and/or the reference circuit is configured so that an effect of the bit line signal value on the second one of the bit lines on the reference signal value on the reference output is equal in size to an effect of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines.

4. An electronic circuit according to claim 1, wherein the reference circuit comprises a resistive element coupled between the second one of the bit lines and the reference output.

5. An electronic circuit according to claim 4, wherein the reference circuit comprises a current source circuit with a current output coupled to the reference output.

6. An electronic circuit according to claim 1, wherein the memory matrix comprises non-volatile memory cells coupled to the bit lines.

7. An electronic circuit according to claim 1, comprising a detection circuit for determining in which of more than two signal ranges a signal on the first one of the bit lines lies, the detection circuit comprising the differential sense amplifier at least for distinguishing between signals in an adjacent pair of the ranges.

8. An electronic circuit according to claim 1, wherein the memory matrix comprises a plurality of columns of memory cells, each bit line corresponding to a respective column, the electronic circuit comprising a respective reference circuit, a respective differential sense amplifier and a respective cross-coupling circuit for each column, each bit line that corresponds to a particular column being coupled to a first input of the differential sense amplifier for the particular column, the reference circuit for the particular column being coupled to a second input of the differential sense amplifier for the particular column, the cross coupling circuit for the particular column coupling at least the bit line for a further column, which is adjacent to the particular column, to the reference circuit, so that a bit line signal value on the bit line for the further column affects a reference signal value on the reference output of the reference circuit for the particular column.

9. An electronic circuit according to claim 1, wherein the matrix comprises a plurality of groups of columns of memory cells, each bit line corresponding to a respective column, the electronic circuit comprising multiplexing circuits, a respective reference circuit, a respective differential sense amplifier and a respective cross-coupling circuit for each group of columns, the bit lines that correspond to columns in the particular group being coupled to a first input of the differential sense amplifier for the particular group via the multiplexing circuits, the bit lines of columns that are adjacent to any column in the particular group being coupled to the reference circuit for the particular group via the multiplexing circuits, the reference circuit for the particular group being coupled to a second input of the differential sense amplifier for the particular group, the multiplexing circuits being configured to couple selectable ones of the bit lines of the group to the first input of the differential sense amplifier while coupling at least one adjacent bit lines of the selected one of the bit lines to the reference circuit for the particular group.

10. A method of reading data from a memory matrix with a plurality of bit lines, the method comprising

providing a differential sense amplifier with a first and second input;

supplying a signal derived from a first one of the bit lines to the first input;

supplying a reference signal from a reference output of a reference circuit to the second input;

coupling at least a second one of the bit lines, which is adjacent to the first one of the bit lines, to the reference circuit, so that a bit line signal value on the second one of the bit lines affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines.