ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION
First Claim
1. An electronic circuit comprisinga memory matrix with a plurality of columns of memory cells and bit lines coupled to the memory cells in respective ones of the columns;
- a reference circuit with a reference output;
a differential sense amplifier with a first and second input,a circuit for coupling the first input of the differential sense amplifier at least to a first one of the bit lines and the second input of the differential sense amplifier to the reference output;
a cross-coupling circuit, configured to couple at least a second one of the bit lines, which is adjacent to the first one of the bit lines, to the reference circuit, so that a bit line signal value on the second one of the bit lines will affect a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines.
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Accused Products
Abstract
Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).
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Citations
10 Claims
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1. An electronic circuit comprising
a memory matrix with a plurality of columns of memory cells and bit lines coupled to the memory cells in respective ones of the columns; -
a reference circuit with a reference output; a differential sense amplifier with a first and second input, a circuit for coupling the first input of the differential sense amplifier at least to a first one of the bit lines and the second input of the differential sense amplifier to the reference output; a cross-coupling circuit, configured to couple at least a second one of the bit lines, which is adjacent to the first one of the bit lines, to the reference circuit, so that a bit line signal value on the second one of the bit lines will affect a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of reading data from a memory matrix with a plurality of bit lines, the method comprising
providing a differential sense amplifier with a first and second input; -
supplying a signal derived from a first one of the bit lines to the first input; supplying a reference signal from a reference output of a reference circuit to the second input; coupling at least a second one of the bit lines, which is adjacent to the first one of the bit lines, to the reference circuit, so that a bit line signal value on the second one of the bit lines affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value on the second one of the bit lines on a bit line signal value on the first one of the bit lines.
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Specification